Patents by Inventor Naoki Sakurai

Naoki Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040146561
    Abstract: A composition for accelerating fracture healing, which comprises a PDE4 inhibitor as an active ingredient, specifically a composition comprising a PDE4 inhibitor and a biocompatible and biodegradable polymer is provided, which composition, when formulated into a form suitable for local administration such as microsphere preparation, can provide a pharmaceutical composition showing an excellent effect in the early healing of bone fracture. The said composition is useful in the healing of refractory fracture of elderly people and diabetic or osteoporosis patients.
    Type: Application
    Filed: November 24, 2003
    Publication date: July 29, 2004
    Inventors: Naoki Sakurai, Toshiki Takagi, Noriyuki Yanaka, Yuji Horikiri, Takashi Tamura
  • Publication number: 20030216875
    Abstract: A thrust jig with a concave-convex shape is pierced into a food sample to generate and detect an oscillation spectrum and an acoustic spectrum, which is analyzed in main component to calculate a main component value as the texture of the food sample.
    Type: Application
    Filed: March 21, 2003
    Publication date: November 20, 2003
    Applicant: Hiroshima University
    Inventor: Naoki Sakurai
  • Publication number: 20030044825
    Abstract: The present invention is to provide a novel protein and a novel gene which are related to bone metabolism, in particular, differentiation (maturation) of osteoblast or morphological change (retraction), and to disclose a polypeptide which comprises a polypeptide selected from the following (A), (B) and (C), and has a function or an activity selected from the following (i), (ii) and (iii):
    Type: Application
    Filed: May 22, 2002
    Publication date: March 6, 2003
    Inventors: Yuji Imai, Hiroyuki Akatsuka, Eri Kawai, Kenji Omori, Noriyuki Yanaka, Naoki Sakurai
  • Publication number: 20020143080
    Abstract: There is provided a water based ink capable of decolorizing or discoloring written or printed letters or images through an organic solvent or heating, which is used for a writing instrument such as roller balls, markers, etc., printing inks, ink jets and the like.
    Type: Application
    Filed: October 23, 2001
    Publication date: October 3, 2002
    Applicant: ZEBRA CO., LTD
    Inventors: Satoru Yui, Naoki Sakurai, Koichi Ito
  • Patent number: 6180966
    Abstract: A trench gate type semiconductor device with a current sensing cell is composed so that the orientation of crystal face at side walls of trenches forming channels of trench gates in a main cell is equal or almost equal, or equivalent or almost equivalent to the orientation of crystal face at side walls of trenches forming channels of trench gates in a current sensing cell, which brings the same performance to the main and sense cells, whereby the high accuracy current sensing can be realized.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: January 30, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Kohno, Naoki Sakurai, Mutsuhiro Mori
  • Patent number: 6144046
    Abstract: An inverter apparatus constituted by one or more series connections of plural semiconductor devices each having a pair consisting of an insulated gate bipolar transistor, and a diode, both of which are in a reverse parallel connection with each other, wherein the resistivity of the base layer of the lowest impurity concentration in the diode is lower than that of the base layer of the lowest impurity concentration in the insulated gate bipolar transistor, and wherein a breakdown voltage of said insulated gate bipolar transistor at the time of switching from a conduction state to a blocking state is lower than a breakdown voltage of said insulated gate bipolar transistor and said diode at the time of the blocking state.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: November 7, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Koumei Hanaoka, Naoki Sakurai, Mutsuhiro Mori
  • Patent number: 5977606
    Abstract: A dielectric isolated high voltage semiconductor device having an arrangement for extending a depletion layer of a main junction beyond an insulating layer containing an island to a semiconductor supporter by applying the same reverse biasing voltage to the supporter and the islands. That is, in the structure, an electrode is provided at the back surface of the supporter and connected to a main electrode of the selected island. The above-mentioned main junction is the pn junction to which the reverse biasing voltage for securing the withstand voltage of the semiconductor device is applied. The device is structured, also, with high impurity concentration regions for preventing a depletion layer, formed during a reverse biasing of the main junction of a circuit element of an island, from extending into adjacently disposed islands.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: November 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Yoshitaka Sugawara
  • Patent number: 5962877
    Abstract: An inverter with an improved semiconductor device is provided having a pn junction composed of a first semiconductor layer made of a first conductivity type semiconductor and a second semiconductor layer made of a second conductivity type semiconductor having a wider band-gap than that of the first semiconductor layer.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: October 5, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Masahiro Nagasu
  • Patent number: 5877518
    Abstract: A semiconductor switching device is provided having a pn junction composed of a first semiconductor layer made of a first conductivity type semiconductor and a second semiconductor layer made of a second conductivity type semiconductor having a wider band-gap than that of the first semiconductor layer.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: March 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Masahiro Nagasu
  • Patent number: 5747829
    Abstract: A dielectric isolated high voltage semiconductor device having an arrangement for extending a depletion layer of a main junction beyond an insulating layer containing an island to a semiconductor supporter by applying the same reverse biasing voltage to the supporter and the islands. That is, in the structure, an electrode is provided at the back surface of the supporter and connected to a main electrode of the selected island. The above-mentioned main junction is the pn junction to which the reverse biasing voltage for securing the withstand voltage of the semiconductor device is applied.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: May 5, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Yoshitaka Sugawara
  • Patent number: 5701018
    Abstract: The present invention provides a semiconductor device comprising, at least a pair of an insulated gate bipolar transistor, and a diode, both of which are in a reverse parallel connection with each other, wherein the resistivity of the base layer of the lowest impurity concentration in the diode is lower than that of the base layer of the lowest impurity concentration in the insulated gate bipolar transistor, and wherein a breakdown voltage of said insulated gate bipolar transistor at the time of switching from conduction state to blocking state is lower than a breakdown voltage of said insulated gate bipolar transistor and said diode at the time of blocking state.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: December 23, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Koumei Hanaoka, Naoki Sakurai, Mutsuhiro Mori
  • Patent number: 5631494
    Abstract: A circuit connecting a sub-IGBT element S.sub.2 having a smaller current capacity and a smaller saturated current than the main IGBT element S.sub.1 and a resistance R.sub.1 in series is connected to the main IGBT element S.sub.1 in parallel, a MOSFET element S.sub.3 being connected between the gate electrode of the sub-IGBT element S.sub.2 and the emitter electrode of the main IGBT element S.sub.1, a delay element being connected between the gate electrode of the sub-IGBT element S.sub.2 and the gate electrode of the main IGBT element S.sub.1. In normal operation, the ON-state voltage is small and low loss can be realized. In the event of a short-circuit accident, the sub-IGBT element S.sub.2 detects the short-circuit before the main IGBT element S.sub.1 turns on to prevent an over-current from flowing in the main IGBT element S.sub.1, which substantially improves the short-circuit resistivity of the semiconductor device.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: May 20, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Yoshitaka Sugawara
  • Patent number: 5463243
    Abstract: A dielectric isolated high voltage semiconductor device having an arrangement for extending a depletion layer of a main junction beyond an insulating layer containing an island to a semiconductor supporter by applying the same reverse biasing voltage to the supporter and the islands. That is, in the structure, an electrode is provided at the back surface of the supporter and connected to a main electrode of the selected island. The above-mentioned main junction is the pn junction to which the reverse biasing voltage for securing the withstand voltage of the semiconductor device is applied.
    Type: Grant
    Filed: November 5, 1993
    Date of Patent: October 31, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Yoshitaka Sugawara
  • Patent number: 5412558
    Abstract: A semiconductor integrated circuit unit, suitable for the control of a motor, has an integrated structure within the same semiconductor substrate, comprising an inverter circuit, drive circuits for driving the switching elements of the inverter circuit, an internal power source circuit for supplying power to the drive circuits which drive the upper arm side of the inverter circuit, and a logical circuit for transmitting a signal to the drive circuits which drive the upper arm side of the inverter circuit.
    Type: Grant
    Filed: September 7, 1993
    Date of Patent: May 2, 1995
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semiconductor, Ltd.
    Inventors: Naoki Sakurai, Mutsuhiro Mori, Hidetoshi Arakawa, Kenichi Onda, Hideki Miyazaki, Akihiko Kanouda
  • Patent number: 5374554
    Abstract: A microorganism derived from a host microorganism capable of producing d-biotin by introducing a recombinant plasmid being incorporated with a biotin gene cloned from a microorganism of the genus Serratia capable of producing d-biotin and further integrating an exogenous biotin gene into the chromosome, and a process for preparing d-biotin which comprises cultivating the microorganism in a culture medium so that d-biotin is formed and accumulated in the culture medium and collecting the d-biotin. The microorganism of the invention has an extremely high productivity of d-biotin, and hence, d-biotin can be produced in a large amount by cultivating the microorganism of the invention.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: December 20, 1994
    Assignee: Tanabe Seiyaku Co., Ltd.
    Inventors: Saburo Komatsubara, Yuji Imai, Makoto Masuda, Naoki Sakurai
  • Patent number: 5343052
    Abstract: A lateral insulated-gate bipolar transistor has a drift region having therein a base layer and a collector layer. An emitter layer is formed in the base layer. A gate electrode structure, comprising a control electrode and gate insulating layer, contacts the base layer, and also contacts the drift layer and the emitter layer. An emitter electrode contacts the emitter layer, and also the base layer, and a collector electrode contacts the collector layer. The emitter and collector electrodes are elongate and the ratio of their resistances per unit length is in the range of 0.5 to 2.0. This reduces the possibility of a localized high current density along the electrodes, thereby reducing the risk of latch-up due to parasitic thyristors. The collector and emitter electrodes may be of the same width and thickness, or of different widths and thicknesses, or may each have an auxiliary part (for example, in a multi-layer wiring arrangement), so that their resistances per unit length are in the desired range.
    Type: Grant
    Filed: July 24, 1992
    Date of Patent: August 30, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Tosifumi Oohata, Mutsuhiro Mori, Naoki Sakurai
  • Patent number: 5278443
    Abstract: A semiconductor device includes a diode having a Schottky barrier and a MOS transistor integrally formed in one and the same semiconductor substrate in which the diode and MOS transistor have their main electrode in common use. The diode has a first diode portion having a pn junction in a current-passing direction and a second diode portion having a combination of the Schottky barrier and another pn junction in the current passing direction.
    Type: Grant
    Filed: November 5, 1992
    Date of Patent: January 11, 1994
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semiconductor, Ltd.
    Inventors: Mutsuhiro Mori, Yasumiti Yasuda, Naoki Sakurai, Hidetoshi Arakawa, Hiroshi Owada
  • Patent number: 5274541
    Abstract: In a module using a high-speed switching element such as an IGBT for a high-speed inverter, a matching condition is established between the switching characteristic of the IGBT and the recovery characteristic of the diode to be connected thereto in an anti-parallel fashion. As a result, the oscillating voltage appearing in the inverter circuit is suppressed to prevent erroneous operation of the inverter system.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: December 28, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Shin Kimura, Yasuo Matsuda, Norikazu Tokunaga, Mutsuhiro Mori, Toshiki Kurosu, Yutaka Suzuki, Naoki Sakurai, Yasumichi Yasuda, Tomoyuki Tanaka, Kenichi Onda
  • Patent number: 5253156
    Abstract: A semiconductor integrated circuit unit, suitable for the control of a motor, has an integrated structure within the same semiconductor substrate, comprising an inverter circuit, drive circuits for driving the switching elements of the inverter circuit, an internal power source circuit for supplying power to the drive circuits which drive the upper arm side of the inverter circuit, and a logical circuit for transmitting a signal to the drive circuits which drive the upper arm side of the inverter circuit.
    Type: Grant
    Filed: January 29, 1991
    Date of Patent: October 12, 1993
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semi-Conductor, Ltd.
    Inventors: Naoki Sakurai, Mutsuhiro Mori, Hidetoshi Arakawa, Kenichi Onda, Hideki Miyazaki, Akihiko Kanouda
  • Patent number: 5166760
    Abstract: A semiconductor device is provided wherein a first diode having a pn junction and a second diode having a combination of a Schottky barrier and a pn junction in a current-passing direction are provided side by side in a direction perpendicular to the current-passing direction. When a forward current with a current density J.sub.F is passed into the second diode, the relation ##EQU1## is established in a forward voltage V.sub.F range of 0.1 (V) to 0.3 (V), where k represents the Boltzmann constant (.apprxeq.1.38.times.10.sup.-23 J/K), T represents the absolute temperature, and q represents the quantity of electron charges (.apprxeq.1.6.times.10.sup.-19 C).
    Type: Grant
    Filed: February 11, 1992
    Date of Patent: November 24, 1992
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semiconductor Ltd.
    Inventors: Mutsuhiro Mori, Yasumiti Yasuda, Naoki Sakurai, Hidetoshi Arakawa, Hiroshi Owada