Patents by Inventor Naoki Tega
Naoki Tega has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978794Abstract: In a SiC power MISFET having a lateral surface of a trench formed in an upper surface of a SiC epitaxial substrate as a channel region, a silicon carbide semiconductor device having low resistance, high performance, and high reliability is realized. As a means therefor, a SiC power MISFET is formed as an island-shaped unit cell on an upper surface of an n-type SiC epitaxial substrate that is provided with a drain region on a bottom surface thereof, the SiC power MISFET including: an n-type current diffusion region that surrounds a p-type body layer contact region and an n-type source region in the indicated order in a plan view; a p-type body layer and an n-type JFET region; a trench that is formed on the body layer so as to span between the source region and the current diffusion region adjacent each other in a first direction and extends in the first direction; and a gate electrode embedded in the trench with a gate insulating film therebetween.Type: GrantFiled: October 24, 2019Date of Patent: May 7, 2024Assignee: HITACHI, LTD.Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe, Yuki Mori, Digh Hisamoto
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Patent number: 11967624Abstract: Abnormal generation of heat of a power MOSFET is detected to improve the reliability of a semiconductor device. As its means, in a power MOSFET having a drain electrode on the side of a back surface of a semiconductor substrate and a source pad on the side of a main surface of the semiconductor substrate, two gate pads electrically connected to a gate pad connected to a gate electrode of the power MOSFET are formed on the side of the main surface of the semiconductor substrate. Further, there is provided a voltmeter connected in parallel with each of two current paths which connect the two gate pads and a gate driver.Type: GrantFiled: October 17, 2019Date of Patent: April 23, 2024Assignee: HITACHI, LTD.Inventors: Naoki Tega, Digh Hisamoto, Takeru Suto
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Publication number: 20230395710Abstract: A semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a body region of a second conductivity type disposed above the drift region, a source region of the first conductivity type disposed above the body region, and a first contact region and a second contact region each having a higher concentration of second conductivity-type impurities than the body region. The first contact region is located in an active region, and reaches the body region beyond the source region. The second contact region is located in an intermediate region, reaches the body region beyond the source region, and extends around the source region along a peripheral edge of the source region. Concentration distributions of the second conductivity-type impurities in a depth direction of the first contact region and the second contact region match with each other.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Inventors: Naoki TEGA, Takuma KATANO
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Patent number: 11527615Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.Type: GrantFiled: October 27, 2020Date of Patent: December 13, 2022Assignee: Hitachi, Ltd.Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe, Hiroshi Miki
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Publication number: 20220115512Abstract: Abnormal generation of heat of a power MOSFET is detected to improve the reliability of a semiconductor device. As its means, in a power MOSFET having a drain electrode on the side of a back surface of a semiconductor substrate and a source pad on the side of a main surface of the semiconductor substrate, two gate pads electrically connected to a gate pad connected to a gate electrode of the power MOSFET are formed on the side of the main surface of the semiconductor substrate. Further, there is provided a voltmeter connected in parallel with each of two current paths which connect the two gate pads and a gate driver.Type: ApplicationFiled: October 17, 2019Publication date: April 14, 2022Inventors: Naoki Tega, Digh Hisamoto, Takeru Suto
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Publication number: 20220059690Abstract: In a SiC power MISFET having a lateral surface of a trench formed in an upper surface of a SiC epitaxial substrate as a channel region, a silicon carbide semiconductor device having low resistance, high performance, and high reliability is realized. As a means therefor, a SiC power MISFET is formed as an island-shaped unit cell on an upper surface of an n-type SiC epitaxial substrate that is provided with a drain region on a bottom surface thereof, the SiC power MISFET including: an n-type current diffusion region that surrounds a p-type body layer contact region and an n-type source region in the indicated order in a plan view; a p-type body layer and an n-type JFET region; a trench that is formed on the body layer so as to span between the source region and the current diffusion region adjacent each other in a first direction and extends in the first direction; and a gate electrode embedded in the trench with a gate insulating film therebetween.Type: ApplicationFiled: October 24, 2019Publication date: February 24, 2022Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe, Yuki Mori, Digh Hisamoto
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Patent number: 11088276Abstract: A plurality of trench gate electrodes are formed from an upper surface to reach an intermediate depth of an n-type SiC epitaxial substrate including an n-type drain region on a lower surface and an n-type source region on an upper surface in contact with the source region to be arranged in a direction along the upper surface. Here, at least three side surfaces among four side surfaces of each of the trench gate electrodes having a rectangular planar shape are in contact with a p-type body layer below the source region. In addition, a JFET region in the SiC epitaxial substrate and a source electrode connected to the source region immediately above the JFET region extend along a direction in which the plurality of trench gate electrodes are arranged.Type: GrantFiled: July 1, 2020Date of Patent: August 10, 2021Assignee: HITACHI, LTD.Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe
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Publication number: 20210143255Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.Type: ApplicationFiled: October 27, 2020Publication date: May 13, 2021Applicant: HITACHI, LTD.Inventors: Takeru SUTO, Naoki TEGA, Naoki WATANABE, Hiroshi MIKI
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Publication number: 20210005746Abstract: A plurality of trench gate electrodes are formed from an upper surface to reach an intermediate depth of an n-type SiC epitaxial substrate including an n-type drain region on a lower surface and an n-type source region on an upper surface in contact with the source region to be arranged in a direction along the upper surface. Here, at least three side surfaces among four side surfaces of each of the trench gate electrodes having a rectangular planar shape are in contact with a p-type body layer below the source region. In addition, a JFET region in the SiC epitaxial substrate and a source electrode connected to the source region immediately above the JFET region extend along a direction in which the plurality of trench gate electrodes are arranged.Type: ApplicationFiled: July 1, 2020Publication date: January 7, 2021Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe
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Patent number: 10790386Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, and an n-type third semiconductor region. A trench is formed having a gate electrode therein in which the bottom face of the trench contacts the p-type semiconductor region. A metal layer is electrically connected to the third semiconductor region, and a source electrode electrically connects the second semiconductor region and the metal layer to each other.Type: GrantFiled: December 11, 2018Date of Patent: September 29, 2020Assignee: HITACHI, LTD.Inventors: Yuan Bu, Hiroshi Miki, Naoki Tega, Naoki Watanabe, Digh Hisamoto, Takeru Suto
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Publication number: 20190229211Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, an n-type third semiconductor region, a trench having a first side face and a second side face opposing to each other and a third side face intersecting with the first side face and the second side face, a gate electrode formed in the trench with a gate insulating film interposed therebetween, a metal layer electrically connected to the third semiconductor region, and a source electrode electrically connecting the second semiconductor region and the metal layer to each other.Type: ApplicationFiled: December 11, 2018Publication date: July 25, 2019Applicant: HITACHI, LTD.Inventors: Yuan BU, Hiroshi MIKI, Naoki TEGA, Naoki WATANABE, Digh HISAMOTO, Takeru SUTO
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Patent number: 10290704Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.Type: GrantFiled: February 12, 2015Date of Patent: May 14, 2019Assignee: HITACHI, LTD.Inventors: Naoki Tega, Naoki Watanabe, Shintaroh Sato
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Patent number: 10229974Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.Type: GrantFiled: May 18, 2015Date of Patent: March 12, 2019Assignee: HITACHI, LTD.Inventors: Mieko Matsumura, Junichi Sakano, Naoki Tega, Yuki Mori, Haruka Shimizu, Keisuke Kobayashi
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Publication number: 20180331174Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.Type: ApplicationFiled: February 12, 2015Publication date: November 15, 2018Inventors: Naoki TEGA, Naoki WATANABE, Shintaroh SATO
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Patent number: 10062759Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.Type: GrantFiled: March 29, 2013Date of Patent: August 28, 2018Assignee: HITACHI, LTD.Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
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Patent number: 10032871Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.Type: GrantFiled: March 29, 2013Date of Patent: July 24, 2018Assignee: HITACHI, LTD.Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
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Patent number: 9960259Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.Type: GrantFiled: January 19, 2015Date of Patent: May 1, 2018Assignee: HITACHI, LTD.Inventors: Naoki Tega, Naoki Watanabe, Shintaroh Sato
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Publication number: 20180090574Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.Type: ApplicationFiled: May 18, 2015Publication date: March 29, 2018Inventors: Mieko MATSUMURA, Junichi SAKANO, Naoki TEGA, Yuki MORI, Haruka SHIMIZU, Keisuke KOBAYASHI
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Patent number: 9825166Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.Type: GrantFiled: January 23, 2013Date of Patent: November 21, 2017Assignee: HITACHI, LTD.Inventors: Naoki Tega, Digh Hisamoto, Satoru Akiyama, Takashi Takahama, Tadao Morimoto, Ryuta Tsuchiya
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Publication number: 20170330961Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.Type: ApplicationFiled: January 19, 2015Publication date: November 16, 2017Applicant: Hitachi, Ltd.Inventors: Naoki TEGA, Naoki WATANABE, Shintaroh SATO