Abstract: The high-speed barrier synchronization is completed among multiprocessors by saving overhead for parallel process without addition of a particular hardware mechanism. That is, the barrier synchronization process is performed by allocating the synchronization flag area, on the shared memory, indicating the synchronization point where the execution of each processor for completing the barrier synchronization is completed, updating the synchronization flag area with the software in accordance with the executing condition, and comparing, with each processor, the synchronization flag area of the other processors which takes part in the barrier synchronization.

Abstract: A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for storing bus-splitting information are provided in a directory control circuit 150 that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network. Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.

Abstract: N shared data registers are provided for N+1 processors, respectively. For allowing all the processors to read the same data from the shared data registers, the processors are connected by interprocessor communication channels. The processors are classified into a master processor and subordinate processors. All data writing into the shared data registers are executed from the master processor. Further, data writing into the shared data registers from the subordinate processor is executed from the master processor after a write request is sent to the master processor.

Abstract: A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for storing bus-splitting information are provided in a directory control circuit 150 that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network. Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.

Abstract: The high-speed barrier synchronization is completed among multiprocessors by saving overhead for parallel process without addition of a particular hardware mechanism. That is, the barrier synchronization process is performed by allocating the synchronization flag area, on the shared memory, indicating the synchronization point where the execution of each processor for completing the barrier synchronization is completed, updating the synchronization flag area with the software in accordance with the executing condition, and comparing, with each processor, the synchronization flag area of the other processors which takes part in the barrier synchronization.

Abstract: A parallel or grid computing system that having a plurality of nodes and achieves job scheduling for the nodes with a view toward system efficiency optimization. The parallel or grid computing system has a plurality of nodes for transmitting and receiving data and a communication path for exchanging data among the nodes, which are either a transmitting node for transmitting data or a receiving node for processing a job dependent on transmitted data, and further has a time measuring means for measuring the time interval between the instant at which data is called for by a job and the instant at which the data is transmitted from a transmitting node to a receiving node, a time counting means for adding up the measured wait time data about each job, and a job scheduling means for determining the priority of jobs in accordance with the counted wait time and for scheduling jobs.

Abstract: N shared data registers are provided for N+1 processors, respectively. For allowing all the processors to read the same data from the shared data registers, the processors are connected by interprocessor communication channels. The processors are classified into a master processor and subordinate processors. All data writing into the shared data registers are executed from the master processor. Further, data writing into the shared data registers from the subordinate processor is executed from the master processor after a write request is sent to the master processor.

Abstract: A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.

Abstract: A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.

Abstract: A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Abstract: A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.

Abstract: Plural instruction processors define part of a main memory as a broadcast area and each have a broadcast area cache for the broadcast area only. An exclusive line which interconnects the broadcast area caches is provided; in order to reflect the result of data updating by a store instruction issued by an instruction processor for the broadcast area, the store instruction is automatically sent to all broadcast area caches for data updating. The other data-receiving instruction processors receive the data by means of a load instruction.

Abstract: Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.

Abstract: Multiple parallel-job scheduling method and apparatus are provided which can improve the utilization of all processors in a system when a plurality of parallel jobs are executed concurrently. A plurality of processors constituting a computer system and each having the equal function are logically categorized into serial processors for executing a serial computing part or a parallel computing part of a parallel job and a parallel processor group consisting of multiple processors for executing the parallel computing part of the parallel job in parallel. In order that the parallel processors are shared by a plurality of parallel jobs, a synchronization range indicator is provided which can control by program whether the parallel processors are available in correspondence to the respective serial processors.

Abstract: To realize interprocessor data transfer with the data receive area not fixed in the real memory and with less overhead for synchronization, the send node sends to the destination node, data, a virtual address of a receive area, an address of a receive control flag, a comparison value, and a comparison method. Network adaptor in the destination node judges whether the transfer condition is fulfilled, based on the comparison value, the comparison method and the semaphore in the receive control flag designated by the receive control flag address. Network adaptor further detects whether the receive area of the virtual address is in the main storage, based on the virtual address and the address translation table. The send data is stored in the receive buffer provided in the area for OS, when the above-mentioned condition is not fulfilled or the receive area is not in the main storage.

Abstract: An information processing system is connected to a common storage and executes programs by use of processors. This system includes a common storage; a plurality of processors, connected to the common storage.

Abstract: To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.

Abstract: A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Abstract: A main memory shared by plural processing units in a parallel computer system is composed of plural partial main memories. A directory for each data line of the main memory is generated after the data line has been cached in one of the processing units. The directory is held in one of the partial main memories in place of the data line. The directory indicates a processing unit which has cached the data line. A status bit C provided for the data line is set. If a subsequent read request is given to the data line, the status C bit is checked and the directory is used to identify a processing unit that has cached the data line. The request is transferred to the identified processing unit, and the data line is transferred from that processing unit to the processing unit that has issued the request. If a processing unit that has cached the data line has replaced the data line, it is checked if there is a processing unit that has cached the data line.