Abstract: An apparatus for communication includes a transmission chain, an interference suppressor and a reception chain. The transmission chain is configured to transmit a transmitted signal. The interference suppressor is configured to produce suppression signals, by filtering reference signals drawn from the transmission chain. At least one of the reference signals is filtered in a frequency domain. The reception chain is configured to receive a signal distorted by at least an attenuated and delayed replica of the transmitted signal. The transmitted signal and the received signal are (i) synchronized in time and (ii) each includes one or more subcarriers selected from a common subcarrier-resource. The reception chain is further configured to process the received signal up to selected points, to subtract the suppression signals from the received signal at the selected points to produce an interference-suppressed signal, and to recover data carried in the received signal from the interference-suppressed signal.

Abstract: An apparatus includes a transmitter, a receiver and a combining element. The transmitter includes multiple coupling devices coupled to a coaxial network via multiple respective ports, and is configured to transmit multiple transmit signals via the coupling devices, and to receive from the coaxial network via the multiple coupling devices multiple reception signals. The receiver is configured to receive a combined signal of the multiple reception signals, interfered by multiple respective interfering signals that originate from the multiple transmit signals, and to process the combined signal to recover data carried in the reception signals. The combining element, included in at least one of the transmitter and the receiver, is configured to receive the multiple reception signals from the respective couplers, and to generate the combined signal with a suppressed level of the interference signals by setting at least a phase of at least one of the reception signals.

Abstract: An apparatus for communication includes a transmission chain, an interference suppressor and a reception chain. The transmission chain is configured to transmit a transmitted signal. The interference suppressor is configured to produce suppression signals, by filtering reference signals drawn from the transmission chain. At least one of the reference signals is filtered in a frequency domain. The reception chain is configured to receive a signal distorted by at least an attenuated and delayed replica of the transmitted signal. The transmitted signal and the received signal are (i) synchronized in time and (ii) each includes one or more subcarriers selected from a common subcarrier-resource. The reception chain is further configured to process the received signal up to selected points, to subtract the suppression signals from the received signal at the selected points to produce an interference-suppressed signal, and to recover data carried in the received signal from the interference-suppressed signal.

Abstract: A digital synthesis channelizer includes a memory buffer and circuitry. The memory buffer stores samples of N input signals having a sampling rate Fsi. The N input signals are processed, prior to storing in the memory buffer, by an N-point time-frequency transform module. The circuitry includes at least P filters derived from a Low-Pass Filter whose stopband frequency depends on Fsi. The circuitry is configured to set a sampling time according to a predefined output sampling rate Fso=?·Fsi, ? being a predefined rate-conversion ratio, to select based on the sampling time one or more filters out of the at least P filters, and using the selected one or more filters, to generate, from at least some of the samples in the memory buffer, a filtered and interpolated output sample of an output signal that sums N digitally resampled by ? and frequency-shifted versions of the respective N input signals.

Abstract: An apparatus for communication includes a transmission chain, an interference suppressor and a reception chain. The transmission chain is configured to transmit a transmitted signal. The interference suppressor is configured to produce suppression signals, by filtering reference signals drawn from the transmission chain. At least one of the reference signals is filtered in a frequency domain. The reception chain is configured to receive a signal distorted by at least an attenuated and delayed replica of the transmitted signal. The transmitted signal and the received signal are (i) synchronized in time and (ii) each includes one or more subcarriers selected from a common subcarrier-resource. The reception chain is further configured to process the received signal up to selected points, to subtract the suppression signals from the received signal at the selected points to produce an interference-suppressed signal, and to recover data carried in the received signal from the interference-suppressed signal.

Abstract: A digital synthesis channelizer includes a memory buffer and circuitry. The memory buffer stores samples of N input signals having a sampling rate FSI. The N input signals are processed, prior to storing in the memory buffer, by an N-point time-frequency transform module. The circuitry includes at least P filters derived from a Low-Pass Filter whose stopband frequency depends on Fsi. The circuitry is configured to set a sampling time according to a predefined output sampling rate Fso=?·Fsi, ? being a predefined rate-conversion ratio, to select based on the sampling time one or more filters out of the at least P filters, and using the selected one or more filters, to generate, from at least some of the samples in the memory buffer, a filtered and interpolated output sample of an output signal that sums N digitally resampled by ? and frequency-shifted versions of the respective N input signals.

Abstract: An apparatus includes a transmitter, a receiver and a combining element. The transmitter includes multiple coupling devices coupled to a coaxial network via multiple respective ports, and is configured to transmit multiple transmit signals via the coupling devices, and to receive from the coaxial network via the multiple coupling devices multiple reception signals. The receiver is configured to receive a combined signal of the multiple reception signals, interfered by multiple respective interfering signals that originate from the multiple transmit signals, and to process the combined signal to recover data carried in the reception signals. The combining element, included in at least one of the transmitter and the receiver, is configured to receive the multiple reception signals from the respective couplers, and to generate the combined signal with a suppressed level of the interference signals by setting at least a phase of at least one of the reception signals.

Abstract: An apparatus for communication includes a transmission chain, an interference suppressor and a reception chain. The transmission chain is configured to transmit a transmitted signal. The interference suppressor is configured to produce suppression signals, by filtering reference signals drawn from the transmission chain. At least one of the reference signals is filtered in a frequency domain. The reception chain is configured to receive a signal distorted by at least an attenuated and delayed replica of the transmitted signal. The transmitted signal and the received signal are (i) synchronized in time and (ii) each includes one or more subcarriers selected from a common subcarrier-resource. The reception chain is further configured to process the received signal up to selected points, to subtract the suppression signals from the received signal at the selected points to produce an interference-suppressed signal, and to recover data carried in the received signal from the interference-suppressed signal.

Abstract: A digital receiver includes a memory buffer and circuitry. The memory buffer stores samples of an input signal having a sampling rate Fsi. The circuitry includes P filter-families that each includes N filters derived from a prototype Low-Pass Filter (LPF) whose stopband frequency depends on an output sampling rate Fso=?·Fsi. The circuitry is configured to set a sampling time according to Fso, to select, based on the sampling time, multiple filter-families out of the P filter-families, and to construct, based on the N filters in each of the selected filter-families, N interpolated filters that are each aligned to the sampling time. The circuitry is further configured to calculate N filtered samples by applying the N interpolated filters to the samples in the memory buffer, and to generate a sample for an output signal of a frequency-slice of the input signal, by digitally down-converting the N filtered samples.

Abstract: Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

Abstract: Some demonstrative embodiments include devices, systems and methods of multi-channel processing. For example, a multi-channel data processor may process data of a plurality of channels, the multi-channel data processor is to switch from processing a first channel to processing a second channel of the plurality of channels by performing a context switch during a single clock cycle, the context switch including storing first state context corresponding to a processing state of the first channel and loading previously stored second state context corresponding to a processing state of the second channel.

Abstract: A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. The algorithm is implemented in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. The soft Reed-Solomon (RS) decoding scheme extracts candidate RS symbols and their Log Likelihood Ratios (LLRs) from QAM symbols. The set of highest probable candidate blocks are then chosen and these are decoded using a variant of the Chase algorithm until a valid codeword is detected at the decoder output.

Abstract: A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

Abstract: A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. At 1024-QAM, a receiver is provided in which a signal to noise ratio is reduced by at least about 1 dB relaxing design considerations and specifications for other components in the system including for the tuner. A soft-RS-symbol generation scheme is provided to enable soft-input RC decoding in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. A typical receiver hardware requirement in an FEC module to implement the disclosed scheme may be comparatively modest, e.g., on an order of approximately 50K gates.

Abstract: A novel apparatus for and method of upstream power control for multiple transmit channels. The invention is particularly useful in environments that include two level amplification, wherein the first level corresponds to each channel separately and the second level corresponds to the joint sum of all the channels. When working with two-level amplification, changing the joint sum amplification is permitted during specific time periods known as “CMTS re-configuration time” in the DOCSIS specification. The mechanism functions to maintain an optimal transmit power operating point of the PGA using self-configuration without any need to receive permission from an exterior control entity such as the cable head-end thus bypassing the prior art requirement of waiting for a global reconfiguration time from the CMTS (i.e. when the specification assures that there is sufficient time to change the PGA gain).

Abstract: A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to many up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.

Abstract: Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

Abstract: A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of the plurality of ADCs. Then the timing mismatch estimation unit calculates a cost function for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit further calculates a gradient for each of the plurality of ADCs, except the reference ADC.

Abstract: A novel apparatus and method of differential decoding for use in a communication system such as a cable system. The differential decoding mechanism of the present invention enables the use of the Chase algorithm for Reed Solomon (RS) codes (i.e. non-binary codes). The mechanism is well suited for use in systems employing QAM data modulation/demodulation techniques and that also incorporate use of a differential encoder such as in DOCSIS capable cable modem systems. The differential decoding mechanism is operative to analyze the input to the differential decoder and adjust the decoding action accordingly. The mechanism generates the first and second candidate constellation points needed by the Chase algorithm. Considering the differential encoding, there are four possible constellation candidates. The differential decoder reduces these four possible options to two by eliminating from consideration two of them.

Abstract: A timing skew estimation system is disclosed that includes a plurality of interleaved analog-to-digital converter circuits (ADCs), a timing mismatch estimation unit, and a correction unit. The timing mismatch estimation unit calculates a correlation between each of the plurality of ADCs. Then the timing mismatch estimation unit calculates a cost function for each of the plurality of ADCs, except the reference ADC. The timing mismatch estimation unit further calculates a gradient for each of the plurality of ADCs, except the reference ADC.