Abstract: The dye-sensitized solar cell element includes at least one dye-sensitized solar cell (DSC), a first current extracting portion and a second current extracting portion for extracting current from the at least one DSC. The DSC comprises a first electrode having a transparent substrate and a transparent conductive layer provided on the surface of the substrate, a second electrode facing the first electrode and having a metal substrate, an oxide semiconductor layer provided on the first electrode, and an annular sealing portion bonding the first electrode with the second electrode. The first current extracting portion is included in the conductive film of one DSC of the at least one DSC, the second current extracting portion is connected with the metal substrate of the second electrode of one DSC of the at least one DSC, and the first and second current extracting portions are disposed next to each other.

Abstract: In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the jth scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1)th scan line to be selected during the second subframe.

Abstract: In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the jth scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1)th scan line to be selected during the second subframe.

Abstract: The dye-sensitized solar cell element includes at least one dye-sensitized solar cell (DSC), a first current extracting portion and a second current extracting portion for extracting current from the at least one DSC. The DSC comprises a first electrode having a transparent substrate and a transparent conductive layer provided on the surface of the substrate, a second electrode facing the first electrode and having a metal substrate, an oxide semiconductor layer provided on the first electrode, and an annular sealing portion bonding the first electrode with the second electrode. The first current extracting portion is included in the conductive film of one DSC of the at least one DSC, the second current extracting portion is connected with the metal substrate of the second electrode of one DSC of the at least one DSC, and the first and second current extracting portions are disposed next to each other.

Abstract: In one embodiment of the present invention, a driving method of a liquid crystal display device is disclosed.

Abstract: In one embodiment, a liquid crystal display device is disclosed in which a gate driver applies a gate-on pulse so that a second period is longer than a first period. Among gate-on pulses applied before the moment of polarity inversion of a data signal, the last end of the gate-on pulse nearest to the moment of the polarity inversion is earlier than the end time of the horizontal period during which the gate-on pulse is applied. The first period starts at the last end of the gate-on pulse and ends at the end time of the horizontal period during which the gate-on pulse is applied. The second period starts at the moment of the polarity inversion and ends at the moment of the application start of the gate-on pulse nearest to the moment of the polarity inversion among the gate-on pulses applied after the polarity inversion.

Abstract: A gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period.

Abstract: A gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period.

Abstract: The liquid crystal display device of this invention includes picture element regions each defined by a first electrode provided on a first substrate and a second electrode provided on a second substrate so as to oppose the first electrode via a liquid crystal layer sandwiched therebetween. In each of the picture element regions, the first electrode includes a solid portion and a nonsolid portion. The liquid crystal display device further includes a pair of polarizing plates disposed with polarization axes thereof crossing each other substantially perpendicularly. The polarization axis of one of the pair of polarizing plates is substantially parallel to a direction in which the solid portion extends. When a voltage is applied between the first electrode and the second electrode, in each of the picture element regions, liquid crystal molecules of the liquid crystal layer are in a radially-inclined orientation state.

Abstract: In one embodiment, a liquid crystal display device is disclosed in which a gate driver applies a gate-on pulse so that a second period is longer than a first period. Among gate-on pulses applied before the moment of polarity inversion of a data signal, the last end of the gate-on pulse nearest to the moment of the polarity inversion is earlier than the end time of the horizontal period during which the gate-on pulse is applied. The first period starts at the last end of the gate-on pulse and ends at the end time of the horizontal period during which the gate-on pulse is applied. The second period starts at the moment of the polarity inversion and ends at the moment of the application start of the gate-on pulse nearest to the moment of the polarity inversion among the gate-on pulses applied after the polarity inversion.

Abstract: In a liquid crystal display device according to one embodiment of the present invention, when the polarities of the source signal voltages do not change over a plurality of horizontal scanning periods, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the jth row rises before the source signal voltages change to values that correspond to pixels along the jth row. Next, the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the jth row falls, and then the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the kth row (j?k) rises. The polarities of the storage capacitor signal voltages applied to storage capacitor bus lines that correspond to sub-pixels of pixels along the jth row are inverted after the image write pulse of the gate signal supplied to a gate bus line that corresponds to pixels along the kth row rises.

Abstract: In one embodiment of the present invention, a gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period.

Abstract: Provided is an active matrix substrate configured such that: a retention capacitor line (18x) is provided so as to correspond to a space between adjacent pixel regions (5?, 5?); capacitor electrodes (27xa, 27xb) are provided so as to overlap the retention capacitor line (18x); a retention capacitor line (18y) is provided so as to correspond to a space between adjacent pixel region (5?, 5?); capacitor electrodes (27ya, 27yb) are provided so as to overlap the retention capacitor line (18y); a first pixel electrode (17a) provided in the pixel region (5?) is electrically connected to the capacitor electrode (27xa) overlapping one (18x) of adjacent retention capacitor lines (18x, 18y) and a second pixel electrode (17b) provided in the pixel region (5?) is electrically connected to the capacitor electrode (27yb) overlapping the other one (18y) of the two adjacent retention capacitor lines (18x, 18y); and an interconnection line (27ia) for electrically connecting the first pixel electrode (17a) is provided.

Abstract: In one embodiment of the present invention, a liquid crystal display device is disclosed in which a gate driver applies a gate-on pulse so that a second period is longer than a first period. The first period and the second period are defined as follows. Among gate-on pulses applied before the moment of polarity inversion of a data signal, the last end of the gate-on pulse nearest to the moment of the polarity inversion is earlier than the end time of the horizontal period during which the gate-on pulse is applied. The first period starts at the last end of the gate-on pulse and ends at the end time of the horizontal period during which the gate-on pulse is applied. The second period starts at the moment of the polarity inversion and ends at the moment of the application start of the gate-on pulse nearest to the moment of the polarity inversion among the gate-on pulses applied after the polarity inversion.

Abstract: A polishing apparatus has a polishing section (302) configured to polish a substrate and a measurement section (307) configured to measure a thickness of a film formed on the substrate. The polishing apparatus also has an interface (310) configured to input a desired thickness of a film formed on a substrate to be polished and a storage device (308a) configured to store polishing rate data on at least one past substrate therein. The polishing apparatus includes an arithmetic unit (308b) operable to calculate a polishing rate and an optimal polishing time based on the polishing rate data and the desired thickness by using a weighted average method which weights the polishing rate data on a lately polished substrate.

Abstract: Projecting sections controlling alignment directions of liquid crystal molecules are provided on at least one of an active matrix substrate and a counter substrate. When viewed from a direction perpendicular to a surface of the active matrix substrate or of the counter substrate, an outline shape of the projecting sections is constituted by continuously arranging a plurality of unit patterns each having a side in parallel with the polarization axis of the first polarizing plate and a side in parallel with the polarization axis of the second polarizing plate. This makes it possible to provide a liquid crystal panel that performs better display with high contrast by reducing a light leakage during a black display period and by ensuring a light transmittance during a gray level display period and a white display period.

Abstract: The present invention provides a liquid crystal display panel, a liquid crystal display device, and a television receiver, each of which permits shortening of production time, simplification of inventory management of the CF substrate, and reduction in production costs.

Abstract: A first sub-pixel area and a second sub-pixel area that are provided in each of pixel areas so as to sandwich a scanning signal line 2. A first sub-pixel is arranged to include the first sub-pixel area and a section of the counter substrate which section corresponds to the first sub-pixel, area and the second sub-pixel is arranged to include the second sub-pixel area and a section of the counter substrate which section corresponds to the second sub-pixel area. A first alignment control structure is provided in the first sub-pixel and a second alignment control structure is provided in the second sub-pixel. The first alignment control structure (L1 and S1 to S4) provided in one pixel (55x) of two adjacent pixels has a shape obtained by rotating by 180° the first alignment control structure (L11, S11 to S14) provided in the other one pixel (55y) of the two adjacent pixels.

Abstract: In one embodiment of the present invention, a liquid crystal panel driving apparatus is disclosed which sequentially receives pieces of video data for one data signal line, (i) prepares a data string by sorting, in order of outputting, a plurality of pieces of video data inputted in a predetermined period while adding a piece of dummy data to a predetermined position, (ii) assigns one horizontal scanning period to an output of a piece of video data while assigning a dummy scanning period to an output of a piece of dummy data, and (iii) sets one horizontal scanning period shorter than an interval of inputting of pieces of video data. This makes it possible to suppress an increase in vertical display period even though a piece of dummy data is added to inputted video data while a dummy scanning period is assigned thereto.

Abstract: The present invention provides a liquid crystal display panel which can reduce the transmittance and further improve the response speed.