Patents by Inventor Naoto Akiyama
Naoto Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7697356Abstract: A method of testing a semiconductor apparatus performs a function test of reading data from memory cells in SRAM by applying a potential lower than a GND potential to a backgate of an n-type MOS transistor with a drain connected with a storage node and a source connected with the GND potential. Then, the method performs a function test of reading data from memory cells by applying a potential higher than the GND potential to the backgate.Type: GrantFiled: November 27, 2007Date of Patent: April 13, 2010Assignee: NEC Electronics CorporationInventor: Naoto Akiyama
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Publication number: 20080181036Abstract: A method of testing a semiconductor apparatus performs a function test of reading data from memory cells in SRAM by applying a potential lower than a GND potential to a backgate of an n-type MOS transistor with a drain connected with a storage node and a source connected with the GND potential. Then, the method performs a function test of reading data from memory cells by applying a potential higher than the GND potential to the backgate.Type: ApplicationFiled: November 27, 2007Publication date: July 31, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Naoto AKIYAMA
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Patent number: 7328065Abstract: A plurality of electrodes are adapted to be attached on a living body. An electric pulse is output through the electrodes as an electric stimulation to the living body. An analyzer is operable to detect a waveform of the electric pulse and to analyze a parameter of the waveform. A display displays the parameter together with one of the waveform and a model waveform which is an invariable waveform representative of the electric pulse.Type: GrantFiled: December 5, 2003Date of Patent: February 5, 2008Assignee: Nihon Kohden CorporationInventors: Jun Watanabe, Tsutomu Wakabayashi, Naoto Akiyama, Masahiko Inomata
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Patent number: 6947793Abstract: An electrotherapy apparatus for generating first and second waveforms having reversed polarities. When the waveform of the electric energy outputted from the output electrodes 112a and 112b is the positive phase, the inductor 105, electric energy storage section 104, the first switch means 101, output electrode 112a, patient 113, and the output electrode 112b are connected so that these can form the closed circuit. In the case where the waveform of the electric energy outputted from the output electrodes 112a and 112b is the negative phase, when the first switch means 101 is closed, the inductor 105 and the electric energy storage section 104 form the closed circuit, and when the first switch means 101 is opened, the inductor 105 and the electric energy storage section 104 are electrically separated, and the delivery of the electric energy to the output electrodes 112a, and 112b is conducted by the inductor 105.Type: GrantFiled: March 8, 2001Date of Patent: September 20, 2005Assignee: Nihon Kohden CorporationInventors: Naoto Akiyama, Masahiko Inomata, Ikuhiro Tsumura
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Publication number: 20050168895Abstract: The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.Type: ApplicationFiled: April 4, 2005Publication date: August 4, 2005Inventor: Naoto Akiyama
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Patent number: 6891210Abstract: The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.Type: GrantFiled: June 27, 2003Date of Patent: May 10, 2005Assignee: NEC Electronics CorporationInventor: Naoto Akiyama
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Patent number: 6836161Abstract: To provide a semiconductor switch driving circuit in which a stable conducting state and a non-conducting state can be kept, the high-speed switching operation is enabled, a lag of switching timing is minimized and which has a simple circuit, the semiconductor switch driving circuit for driving a semiconductor switch in which multistage switching devices (IGBT) are connected includes a transformer, a primary side and a secondary side and is configured so that voltage between the gate and the emitter of a switching device can be continuously kept positive, voltage between the gate and the emitter can be continuously kept negative, voltage between the gate and the emitter is alternately switched to positive voltage or negative voltage.Type: GrantFiled: March 22, 2001Date of Patent: December 28, 2004Assignee: Nihon Kohden CorporationInventors: Naoto Akiyama, Masahiko Inomata, Ikuhiro Tsumura
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Publication number: 20040162588Abstract: A plurality of electrodes are adapted to be attached on a living body. An electric pulse is output through the electrodes as an electric stimulation to the living body. An analyzer is operable to detect a waveform of the electric pulse and to analyze a parameter of the waveform. A display displays the parameter together with one of the waveform and a model waveform which is an invariable waveform representative of the electric pulse.Type: ApplicationFiled: December 5, 2003Publication date: August 19, 2004Applicant: NIHON KOHDEN CORPORATIONInventors: Jun Watanabe, Tsutomu Wakabayashi, Naoto Akiyama, Masahiko Inomata
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Publication number: 20040004229Abstract: The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.Type: ApplicationFiled: June 27, 2003Publication date: January 8, 2004Applicant: NEC Electronics CorporationInventor: Naoto Akiyama
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Publication number: 20030214015Abstract: The semiconductor device according to the present invention having an LSI circuit and an inductor element formed on the same substrate has an interlayer insulating film formed on the substrate, a first laminated wiring layer formed on the interlayer insulating film and serves as an internal wiring of the LSI circuit, and a second laminated wiring layer formed on the interlayer insulating film and constitutes the inductor element, wherein the first and second laminated wiring layers are mutually different, and no Ti layer which makes contact with an Al alloy layer exists on the second laminated wiring layer.Type: ApplicationFiled: April 30, 2003Publication date: November 20, 2003Applicant: NEC ELECTRONICS CORPORATIONInventor: Naoto Akiyama
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Patent number: 6628492Abstract: The invention has an object of providing a disarm circuit using a semiconductor switch device that can secure the safety of an electrotherapy apparatus by disarming even if the control of the semiconductor switch is disabled because of some cause. Therefore, the disarm circuit is provided with a transformer, its primary side area, its secondary side area, a resistor for disarming and the semiconductor switch device. The secondary side area is characterized in that a resistor for limiting excessive current for automatically turning on the semiconductor switch device by stored electric energy is connected between a positive terminal of an electric energy storage section and the gate of the semiconductor switch device.Type: GrantFiled: May 15, 2001Date of Patent: September 30, 2003Assignee: Nihon Kohden CorporationInventors: Naoto Akiyama, Masahiko Inomata, Ikuhiro Tsumura
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Patent number: 6403467Abstract: In a method for manufacturing a semiconductor device, a first insulation film is grown on a semiconductor substrate, a first interconnect is formed thereover, and a second insulation film is grown over the first insulation film, including the first interconnect. A first connecting via hole, disposed at an edge part of the first interconnect, and a second connecting via hole, disposed at the center part thereof, are then formed, a metal film being additionally grown on the second insulation film, after which chemical metal polishing is used to remove the metal film, over which is formed a second interconnect.Type: GrantFiled: December 14, 1999Date of Patent: June 11, 2002Assignee: NEC CorporationInventor: Naoto Akiyama
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Publication number: 20020030279Abstract: In a method for manufacturing a semiconductor device, a first insulation film is grown on a semiconductor substrate, a first interconnect is formed thereover, and a second insulation film is grown over the first insulation film, including the first interconnect. A first connecting through hole, disposed at an edge part of the first interconnect, and a second connecting through hole, disposed at the center part thereof, are then formed, a metal film being additionally grown on the second insulation film, after which chemical metal polishing is used to remove the metal film, over which is formed a second interconnect.Type: ApplicationFiled: November 21, 2001Publication date: March 14, 2002Inventor: Naoto Akiyama
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Publication number: 20020022867Abstract: The apparatus is structured in such a manner that, when the waveform of the electric energy outputted from the output electrodes 112a and 112b is the positive phase, the inductor 105, electric energy storage section 104, the first switch means 101, output electrode 112a, patient 113, and the output electrode 112b are connected so that these can form the closed circuit, and in the case where the waveform of the electric energy outputted from the output electrodes 112a and 112b is the negative phase, when the first switch means 101 is closed, the inductor 105 and the electric energy storage section 104 form the closed circuit, and when the first switch means 101 is opened, the inductor 105 and the electric energy storage section 104 are electrically separated, and the delivery of the electric energy to the output electrodes 112a, and 112b is conducted by the inductor 105.Type: ApplicationFiled: March 8, 2001Publication date: February 21, 2002Inventors: Naoto Akiyama, Masahiko Inomata, Ikuhiro Tsumura
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Publication number: 20010044640Abstract: To provide a semiconductor switch driving circuit in which a stable conducting state and a non-conducting state can be kept, the high-speed switching operation is enabled, a lag of switching timing is minimized and which has a simple circuit, the semiconductor switch driving circuit for driving a semiconductor switch in which multistage switching devices (IGBT) are connected includes a transformer, a primary side and a secondary side and is configured so that voltage between the gate and the emitter of a switching device can be continuously kept positive, voltage between the gate and the emitter can be continuously kept negative, voltage between the gate and the emitter is alternately switched to positive voltage or negative voltageType: ApplicationFiled: March 22, 2001Publication date: November 22, 2001Inventors: Naoto Akiyama, Masahiko Inomata, Ikuhiro Tsumura
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Publication number: 20010043451Abstract: The invention has an object of providing a disarm circuit using a semiconductor switch device that can secure the safety of an electrotherapy apparatus by disarming even if the control of the semiconductor switch is disabled because of some cause. Therefore, the disarm circuit is provided with a transformer, its primary side area, its secondary side area, a resistor for disarming and the semiconductor switch device. The secondary side area is characterized in that a resistor for limiting excessive current for automatically turning on the semiconductor switch device by stored electric energy is connected between a positive terminal of an electric energy storage section and the gate of the semiconductor switch device.Type: ApplicationFiled: May 15, 2001Publication date: November 22, 2001Applicant: NIHON KOHDEN CORPORATIONInventors: Naoto Akiyama, Masahiko Inomata, Ikuhiro Tsumura
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Publication number: 20010005613Abstract: First NMOS and PMOS transistors for operating high speed, and second NMOS and PMOS transistors for reducing a leak current in an off state, are formed on the same p-type substrate. In a fabricating method, Boron is ion-implanted to the first and second NMOS transistor forming regions of the surface of the substrate to form p well. Subsequently, boron is ion-implanted to only the second NMOS transistor forming region additionally for threshold voltage adjustment to minimize the off-state leak current. Arsenic is ion-implanted to the first and second PMOS transistor forming regions of the surface of the substrate to form n well. Subsequently, Arsenic is ion-implanted only to the second PMOS transistor forming region additionally for threshold voltage adjustment to minimize the off-state leak current.Type: ApplicationFiled: December 21, 2000Publication date: June 28, 2001Inventor: Naoto Akiyama
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Patent number: 6043546Abstract: In the manufacture of a planar channel-type MOS transistor, an n-well is formed in a predetermined region of a p-type semiconductor substrate to define a p-channel transistor region in which element forming regions are located as a p-type active region and a p-type gate electrode. A p-type substrate region adjacent to the p-channel transistor region defines an n-channel transistor region in which element forming regions are located as an n-type active region and an n-type gate electrode. Titanium silicide is formed in self-alignment as an upper layer of each of the p- and n-type active regions and p- and n-type gate electrodes. A boundary of the p- and n-type gate electrodes is a nondoped region where the titanium silicide is formed in an increased thickness as compared to that of the titanium silicide formed on the remaining portion of the gate electrodes.Type: GrantFiled: March 31, 1998Date of Patent: March 28, 2000Assignee: NEC CorporationInventor: Naoto Akiyama