Abstract: A voltage drop Vzs is calculated based on an output current detection value Iac and a virtual synchronous impedance Zs or a corrected virtual synchronous impedance Zs?, and a value obtained by subtracting the voltage drop Vzs from an internal induced voltage Ef is output as a grid voltage command value Vac*. Zs calculation unit 7 limits an output current phase ? so that the output current phase ? is within an effective range by a phase limiter 12a, and calculates the corrected virtual synchronous impedance Zs? based on a limited output current phase ?, the internal induced voltage Ef, a grid voltage detection value Vac and a current limit value Ilim. Accordingly, in grid interconnection power conversion device that controls a virtual synchronous generator, it is possible to continue operation while suppressing an overcurrent and possess a synchronizing power generated by action or working of a virtual synchronous impedance.

Abstract: A display apparatus includes a touch panel functioning as a receiving unit receiving an operation and a display section, and a control section controlling the display section to display a display window including a first display area for displaying a bundle of images of reduced images of respective pages contained in a document file and a second display area for displaying a page image of part of the pages contained in the document file, when an instruction to add a page is received by the touch panel, the control section displays a page image of an added additional page in the second display area and displays a bundle of thumbnail images containing a reduced image of the page image of the additional page in the first display area.

Abstract: A control system is provided for a power conversion system having a power converter that controls a virtual synchronous generator simulating a synchronous generator and interconnected to a power grid. The control system has a virtual synchronous impedance compensation block inputting an output current detection value of the power converter and a set voltage amplitude command value, simulating a voltage drop due to a virtual synchronous impedance, and calculating an output voltage command value and an internal induced voltage according to the simulated voltage drop; a virtual synchronous generator model determining an angular frequency simulating the synchronous generator; and a PCS output voltage control unit performing control so that an output voltage of the power conversion system coincides with the output voltage command value calculated by the virtual synchronous impedance compensation block.

Abstract: A voltage drop Vzs is calculated based on an output current detection value Iac and a virtual synchronous impedance Zs or a corrected virtual synchronous impedance Zs?, and a value obtained by subtracting the voltage drop Vzs from an internal induced voltage Ef is output as a grid voltage command value Vac*. Zs calculation unit 7 limits an output current phase ? so that the output current phase ? is within an effective range by a phase limiter 12a, and calculates the corrected virtual synchronous impedance Zs? based on a limited output current phase ?, the internal induced voltage Ef, a grid voltage detection value Vac and a current limit value Ilim. Accordingly, in grid interconnection power conversion device that controls a virtual synchronous generator, it is possible to continue operation while suppressing an overcurrent and possess a synchronizing power generated by action or working of a virtual synchronous impedance.

Abstract: A vehicle wire harness includes first to third cables to be respectively connected to different connection target objects, a sheath covering all the first to third cables together, and a molded resin member covering a portion of the sheath and a portion of each of the first to third cables. The first to third cables are led out of the molded resin member in different directions from each other.

Abstract: A vehicle wire harness includes first to third cables to be respectively connected to different connection target objects, a sheath covering all the first to third cables together, and a molded resin member covering a portion of the sheath and a portion of each of the first to third cables. The first to third cables are led out of the molded resin member in different directions from each other.

Abstract: To provide a warning system that can issue a stall warning taking a flight environment into account. The warning system according to the present invention is a warning system for an aircraft, for issuing a warning in the case where there is a possibility of the aircraft stalling, and includes a selecting section for selecting one of two or more calculation criteria based on an icing state of the aircraft, a calculating section for calculating a stall angle based on the selected calculation criterion, and a warning section for comparing the calculated stall angle with a current angle of attack of the aircraft and issuing a stall warning if the current angle of attack exceeds the stall angle.

Abstract: A method sets certain downstream traffic scheduling rules at an optical line terminal OLT and certain sleep control rules at optical network units ONUs. Both downstream traffic scheduling rules and sleep control rules are common information owned by both the OLT and ONUs. The method sets the traffic scheduling rules that each ONU is allocated with some time slots every cycle if the ONU has downstream traffic. Rather than using a control message to notify ONUs with their queue status, the method lets ONUs infer whether its downstream queue is empty or not based on downstream traffic scheduling and lets the OLT infer the status of an ONU based on sleep control rules.

Abstract: To provide a warning system that can issue a stall warning taking a flight environment into account. The warning system according to the present invention is a warning system for an aircraft, for issuing a warning in the case where there is a possibility of the aircraft stalling, and includes a selecting section for selecting one of two or more calculation criteria based on an icing state of the aircraft, a calculating section for calculating a stall angle based on the selected calculation criterion, and a warning section for comparing the calculated stall angle with a current angle of attack of the aircraft and issuing a stall warning if the current angle of attack exceeds the stall angle.

Abstract: An interprocedural exception analysis and transformation framework for computer programming languages such as C++ that (1) captures the control-flow induced by exceptions precisely, and (2) transforms the given computer program into an exception-free program that is amenable for precise static analysis, verification, and optimizations.

Abstract: A scalable, computer implemented method for finding subtle flaws in software programs. The method advantageously employs 1) scope bounding which limits the size of a generated model by excluding deeply-nested function calls, where the scope bounding vector is chosen non-monotonically, and 2) automatic specification inference which generates constraints for functions through the effect of a light-weight and scalable global analysis. Advantageously, scalable software model checking is achieved while at the same time finding more bugs.

Abstract: A computer implemented program analysis method employing a set of new abstract domains applicable to non-convex invarients. The method analyzes programs statically using abstract interpretation while advantageously considering non-convex structures and in particular those situations in which an internal region of an unreachable state exists within a larger region of reachable states. The method employs a new set of non-convex domains (donut domains) based upon the notion of an outer convex region of reachable states (Domain D1) and an inner region of unreachable states (Domain D2) which advantageously permits capture of non-convex properties by using convex regions and operations.

Abstract: A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

Abstract: A computer implemented program analysis method employing a set of new abstract domains applicable to non-convex invarients. The method analyzes programs statically using abstract interpretation while advantageously considering non-convex structures and in particular those situations in which an internal region of an unreachable state exists within a larger region of reachable states. The method employs a new set of non-convex domains (donut domains) based upon the notion of an outer convex region of reachable states (Domain D1) and an inner region of unreachable states (Domain D2) which advantageously permits capture of non-convex properties by using convex regions and operations.

Abstract: A computer implemented method for analyzing a computer software program comprising both C++ and C string components, wherein the method includes building a memory model abstraction of any memory used by the program strings. Various memory models are presented that find invalid memory accesses in terms of validity of memory regions and buffer overflows. The model supports analyzing the interaction of C and C++ components—in particular, it focuses on the interaction of C and C++ strings. The conversion of C++ strings to C strings is accomplished through a non-transferable ownership attribute that is to be respected by the C strings. The models can then be analyzed using static analysis techniques such as abstract interpretation and model checking, or through dynamic analysis. In so doing we allow discovery of potential memory safety violations in programs involving conversions between C and C++ strings.

Abstract: A scalable, computer implemented method for finding subtle flaws in software programs. The method advantageously employs 1) scope bounding which limits the size of a generated model by excluding deeply-nested function calls, where the scope bounding vector is chosen non-monotonically, and 2) automatic specification inference which generates constraints for functions through the effect of a light-weight and scalable global analysis. Advantageously, scalable software model checking is achieved while at the same time finding more bugs.

Abstract: A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

Abstract: An interprocedural exception analysis and transformation framework for computer programming languages such as C++ that (1) captures the control-flow induced by exceptions precisely, and (2) transforms the given computer program into an exception-free program that is amenable for precise static analysis, verification, and optimizations.

Abstract: In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has a low testing frequency, an exclusive-OR circuit generates an adjusting clock signal TCLK obtained by multiplying a frequency of a pair of test clock signals which respectively have a phase difference. A DLL circuit inputs the adjusting clock signal TCLK in place to an external clock signal CLK. The counter circuit counts the control clock signal CCLK outputted from the DLL circuit for a predetermined time. A comparator compares a counted value to an expected value and outputs a comparison result. A phase adjusting circuit outputs an adjusting signal to a delay circuit inside the DLL circuit based on the comparison result outputted from the comparator, and adjusts a phase of the control clock signal CCLK outputted from the DLL circuit.

Abstract: An information display device, an information display method, and a program displays, when displaying definition information of an instance method selected by a user, definition information that corresponds to contents of processing of the instance method during runtime. The information display device displays definition information of an instance method selected by a user; wherein the instance method is included in a type that can be referenced during runtime by a variable that references a receiver object of the instance method.