Abstract: To provide an organic electroluminescent element having uniform luminescence properties stable in operation and excellent in life property, an organic electroluminescent element in which a luminescent layer is provided between a positive electrode and a negative electrode, wherein a buffer layer constituted with a transition metal oxide (for example, molybdenum oxide) is provided between the negative electrode and the luminescent layer.

Abstract: An image forming apparatus includes a photoconductor 8 which bears an image to be formed by exposure, a light emission part 600 which emits light for exposing the photoconductor 8 to the light, and a light quantity measuring part 700 which measures the quantity of the light emitted from the light emission part 600 and outputs a light quantity measuring signal. The light quantity measuring signal of the light quantity measuring part 700 is sent through an engine control part 42 to a controller 41, and the quantity of the light emitted from the light emission part 600 is controlled so that the light quantity measuring signal becomes a predetermined value. Here, a sign indicating inclination (change rate) of the light quantity measuring signal of the light quantity measuring part 700 for temperature is matched with a sign indicating inclination (change rate) of sensitivity of the photoconductor 8 for temperature.

Abstract: There is provided a light emitting apparatus for which sealing can be carried out with a simple step using a thermosetting resin as a material for a sealing part, and which has ensured a sufficient gas barrier property without damaging an organic electroluminescence element by heat, and further while using a simple sealing step. The apparatus was configured so as to have a substrate 2, a plurality of light emitting parts formed using a polymer organic electroluminescence material formed on the substrate 2, an electrode (cathode 7) covering the light emitting parts LS, and a sealing part 10 including a thermosetting resin, covering at least the wider region than this electrode (cathode 7).

Abstract: A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers.

Abstract: A semiconductor memory device in which a protection layer is disposed between a silicon storage electrode and a tantalum pentoxide dielectric layer. A conductive material having a larger free energy of oxide formation than that of the tantalum pentoxide is used for forming the protection layer. Therefore, no native oxide film is formed at the interface between the storage electrode and the dielectric layer. As a result, the dielectric constant of the dielectric layer does not decrease even when the dielectric layer is a thin film.

Abstract: A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer.

Abstract: A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor.

Abstract: According to the method of preventing the corrosion of metallic wirings of the present invention, aluminium alloy wirings are formed on the surface of a substrate with the use of photoresists, and the photoresists are then removed. Thereafter, HMDS (hexamethyl disilazine) serving as a surface-active agent or its derivative is supplied to the aluminium alloy wirings to form hydrophobic molecular layers on the lateral walls of the aluminium alloy wirings.

Abstract: A semiconductor memory device in which a storage electrode of a storage capacitor of a memory cell is formed by a selective chemical vapor deposition (CVD) technique. A lithography process is not required when forming the storage electrode. There is no narrowing of the storage electrode pattern and the minimum distance between adjacent storage electrodes can be made smaller than the minimum wiring dimension. The storage capacitance of the semiconductor memory device can be increased and a high storage capacitance is obtained.

Abstract: A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.

Abstract: Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

Abstract: A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.

Abstract: A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer.

Abstract: Disclosed is a semiconductor memory device comprising a semiconductor substrate on which memory cells are formed, each including a switching transistor formed on the semiconductor substrate and a capacitor disposed above the switching transistor. The capacitor has a storage electrode, a cell plate and a capacitor insulating film sandwiched therebetween. The storage electrodes of at least two adjacent memory cells are partly disposed one above the other, with part of the cell plate interposed therebetween. Also disclosed is a semiconductor memory device in which the capacitors of the memory cells are disposed in a trench formed in the semiconductor substrate. The two switching transistors of two adjacent memory cells are located on each island-shaped active region surrounded by the trench. The storage electrodes of the capacitors of the two adjacent memory cells extend side by side around the corresponding active region, with part of the cell plate interposed between the storage electrodes.