Abstract: A data processing apparatus includes bus masters and a memory controller. Each bus master includes a data buffer, and issues a memory command to specify access to the memory and generates first priority information depending on a free space of the data buffer, wherein the first priority information is associated with the memory command and indicates a priority of the memory command. The memory controller determines a processing order of memory commands which are issued by the plurality of bus masters based on the first priority information corresponding to the memory commands, and executes the respective memory commands transferred from the plurality of bus masters in the processing order determined by the processing order determining unit.

Abstract: In a sampling frequency conversion apparatus, an input sample register stores a predetermined number of input samples as an original sequence of input samples for an interpolative operation. A coefficient generating part prepares a first sequence of interpolative coefficients corresponding to an oversampled sequence of input samples which are obtained by inserting nominal input samples of zero values to the input samples stored in the input sample register, and generates a second sequence of interpolative coefficients which are extracted from the first sequence of the interpolative coefficients and which correspond to the original sequence of the input samples. A convolutional operation part convolutes the second sequence of the interpolative coefficients with the original sequence of the input samples so as to output an interpolated sample.

Abstract: An audio signal processor is composed of a data path unit, a mode register and a state machine unit. The data path unit applies one or more arithmetical operation to an audio signal for performing signal processing of the audio signal. The mode register stores mode information specifying the signal processing to be performed by the data path unit. The state machine unit sequentially feeds control signals according to the mode information for enabling the data path unit to apply one or more arithmetical operation to the audio signal so as to perform the signal processing. The performed signal processing is composed of the one or more arithmetical operations, and is specified by the mode information stored in the mode register.

Abstract: In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data amount detection portion detects a remaining data amount of the stored data which remain in the first-in first-out storage. A variable frequency oscillating portion generates an enable signal at a time rate according to frequency control information so as to enable generation of the write request signal or read request signal. A frequency control portion corrects the frequency control information so as to return the remaining data amount to an appropriate value when the remaining data amount detected by the remaining data amount detection portion varies away from the appropriate value toward an upper limit value or varies away from the appropriate value toward a lower limit value.

Abstract: In a sampling frequency conversion apparatus, an input sample register stores a predetermined number of input samples as an original sequence of input samples for an interpolative operation. A coefficient generating part prepares a first sequence of interpolative coefficients corresponding to an oversampled sequence of input samples which are obtained by inserting nominal input samples of zero values to the input samples stored in the input sample register, and generates a second sequence of interpolative coefficients which are extracted from the first sequence of the interpolative coefficients and which correspond to the original sequence of the input samples. A convolutional operation part convolutes the second sequence of the interpolative coefficients with the original sequence of the input samples so as to output an interpolated sample.

Abstract: In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.

Abstract: A data transfer control device and method is devoted to control data transfer (i.e., DMA transfer) between a main memory whose storage capacity is arbitrarily set and a buffer memory (e.g., a FIFO memory) incorporated in a peripheral module, wherein a first register is arranged to store a first value representing a first number of times for transferring m-bit data to suit the storage capacity of the buffer memory, and a second register is arranged to store a second value representing a second number of times for transferring m-bit data to match the amount of transferring data stored in the main memory. A controller is arranged to control transferring of m-bit data based on the first value while controlling writing operations for the buffer memory. It determines the timing to output an interrupt signal to a CPU managing the main memory on the basis of the second value.

Abstract: In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data amount detection portion detects a remaining data amount of the stored data which remain in the first-in first-out storage. A variable frequency oscillating portion generates an enable signal at a time rate according to frequency control information so as to enable generation of the write request signal or read request signal. A frequency control portion corrects the frequency control information so as to return the remaining data amount to an appropriate value when the remaining data amount detected by the remaining data amount detection portion varies away from the appropriate value toward an upper limit value or varies away from the appropriate value toward a lower limit value.

Abstract: A semiconductor memory device has an array of memory cells for memorizing data, an address circuit responsive to an address signal for addressing a memory cell in the array, and a write circuit responsive to a write signal for writing the data into the addressed memory cell. A control circuit is provided for delaying an input timing of the write signal to the write circuit by a given delay amount so as to adjust a timing of writing the data after addressing the memory cell. The control circuit has a register and a variable delay. The register is capable of registering control data for setting the delay amount. The variable delay is provided for delaying the write signal by the set delay amount and outputting the delayed write signal to the write circuit.

Abstract: In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.

Abstract: An audio signal processor is composed of a data path unit, a mode register and a state machine unit. The data path unit applies one or more arithmetical operation to an audio signal for performing signal processing of the audio signal. The mode register stores mode information specifying the signal processing to be performed by the data path unit. The state machine unit sequentially feeds control signals according to the mode information for enabling the data path unit to apply one or more arithmetical operation to the audio signal so as to perform the signal processing. The performed signal processing is composed of the one or more arithmetical operations, and is specified by the mode information stored in the mode register.

Abstract: A semiconductor memory device has an array of memory cells for memorizing data, an address circuit responsive to an address signal for addressing a memory cell in the array, and a write circuit responsive to a write signal for writing the data into the addressed memory cell. A control circuit is provided for delaying an input timing of the write signal to the write circuit by a given delay amount so as to adjust a timing of writing the data after addressing the memory cell. The control circuit has a register and a variable delay. The register is capable of registering control data for setting the delay amount. The variable delay is provided for delaying the write signal by the set delay amount and outputting the delayed write signal to the write circuit.

Abstract: A data transfer control device and method is devoted to control data transfer (i.e., DMA transfer) between a main memory whose storage capacity is arbitrarily set and a buffer memory (e.g., a FIFO memory) incorporated in a peripheral module, wherein a first register is arranged to store a first value representing a first number of times for transferring m-bit data to suit the storage capacity of the buffer memory, and a second register is arranged to store a second value representing a second number of times for transferring m-bit data to match the amount of transferring data stored in the main memory. A controller is arranged to control transferring of m-bit data based on the first value while controlling writing operations for the buffer memory. It determines the timing to output an interrupt signal to a CPU managing the main memory on the basis of the second value.

Abstract: A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of work lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines.

Abstract: A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of word lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines.

Abstract: A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of word lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines.

Abstract: A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of word lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines.