Patents by Inventor Naoya Ichinose

Naoya Ichinose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9442724
    Abstract: A CPU includes a code write unit which writes an interrupt generation code into a page in which the instructions stored in the non-volatile memory are not written, among a plurality of the pages included in an instruction area that is an area of the volatile memory into which the instructions are written, the interrupt generation code being a code for generating a software interrupt, an instruction transfer unit which transfers the instructions from the non-volatile memory to a corresponding page of the volatile memory that is a page in which the interrupt generation code generating the software interrupt is stored when the software interrupt is generated by the interrupt generation code, the instructions being to be stored in the corresponding page, and an instruction execution unit which executes the instructions stored in the instruction area, and when the interrupt generation code is executed, generates a software interrupt.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: September 13, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Toshio Sasaoka, Naoya Ichinose
  • Publication number: 20130318331
    Abstract: A CPU includes a code write unit which writes an interrupt generation code into a page in which the instructions stored in the non-volatile memory are not written, among a plurality of the pages included in an instruction area that is an area of the volatile memory into which the instructions are written, the interrupt generation code being a code for generating a software interrupt, an instruction transfer unit which transfers the instructions from the non-volatile memory to a corresponding page of the volatile memory that is a page in which the interrupt generation code generating the software interrupt is stored when the software interrupt is generated by the interrupt generation code, the instructions being to be stored in the corresponding page, and an instruction execution unit which executes the instructions stored in the instruction area, and when the interrupt generation code is executed, generates a software interrupt.
    Type: Application
    Filed: July 30, 2013
    Publication date: November 28, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Toshio SASAOKA, Naoya ICHINOSE
  • Patent number: 8447899
    Abstract: A device, which has not obtained a resource, can securely obtain a required resource without degradation in response to resource obtainment, and obtains the resource which is exclusively controlled between the device and another device. The device includes: a status detector which detects a status of the other device; a resource obtainer which includes flag information and obtains the resource based on the flag information, the flag information indicating whether the obtainment of the resource is permitted or prohibited; and a determiner which switches the flag information to indicate whether the obtainment is permitted or prohibited, based on the status of the other device detected by the status detector. The resource obtainer is prohibited from obtaining the resource when the flag information indicates that the obtainment is prohibited.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventor: Naoya Ichinose
  • Patent number: 8156363
    Abstract: An information processing device and a mobile terminal include a power consumption calculator which calculates, for each processing executed by the information processing device (or mobile terminal), power consumption information concerning an amount of power consumed by executing each processing. A request generator compares the amount of power indicated by the power consumption information and a remaining amount of power of the information processing device(or mobile terminal), and generates a request to execute predetermined processing according to a result of the comparison. A request processor executes the predetermined processing in response to the generated request.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: April 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Keita Kobayashi, Ryoko Morita, Yusuke Ito, Naoya Ichinose, Shoichi Araki, Osamu Nishimura, Toshio Sasaoka, Yoko Matsushima
  • Publication number: 20110246694
    Abstract: A multi-processor system of the present invention comprises a plurality of processors each configured to lock a shared resource and process a task; each of the processors including a lock wait information storage unit for storing lock wait information indicating whether or not the processor is waiting for acquirement of a lock of the shared resource; and a lock acquirement priority information storage unit for storing lock acquirement priority information indicating a priority according to which the shared resource is acquired; and each of the processors being configured to acquire the lock of the shared resource based on the lock wait information and the lock acquirement priority information.
    Type: Application
    Filed: June 10, 2011
    Publication date: October 6, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Naoya Ichinose
  • Publication number: 20110119411
    Abstract: A device, which has not obtained a resource, can securely obtain a required resource without degradation in response to resource obtainment, and obtains the resource which is exclusively controlled between the device and another device. The device includes: a status detecting unit (15) which detects a status of the other device; a resource obtaining unit (13) which includes flag information and obtains the resource based on the flag information, the flag information indicating whether the obtainment of the resource is permitted or prohibited; and a determining unit (16) which switches the flag information to indicate whether the obtainment is permitted or prohibited, based on the status of the other device detected by the status detecting unit (15). The resource obtainment unit (13) is prohibited from obtaining the resource when the flag information indicates that the obtainment is prohibited.
    Type: Application
    Filed: January 26, 2011
    Publication date: May 19, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Naoya ICHINOSE
  • Patent number: 7865706
    Abstract: According to a generated instruction, the present invention provides an information processing method for performing processing by using a CPU that comprises at least one register. The method comprises the steps of: judging whether or not each of the registers is valid in the instruction; identifying a register whose value is changed by an interrupt processing generated in the instruction; and calculating a number of registers to be evacuated in the interrupt processing based on valid judgment information of the register and identification information of the register whose value is changed by the interrupt processing, and determining whether or not the interrupt processing is permitted based on a calculation result thereof.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 4, 2011
    Assignee: Panasonic Corporation
    Inventor: Naoya Ichinose
  • Publication number: 20090013204
    Abstract: An information processing device, for use in a mobile terminal unable to obtain power consumption information from an external source, which can estimate, based on an actual performance value, a battery life, power consumption for processing that changes depending on the usage by the user, and so on, and ensures execution of processing specified by the user for a specified period of time, the information processing device comprising a power consumption calculating unit which calculates, for each processing executed by the information processing device, power consumption information concerning an amount of power consumed by executing each processing; a request generating unit which compares the amount of power indicated by the power consumption information and a remaining amount of power of the information processing device, and generates a request to execute predetermined processing according to a result of the comparison; and a request processing unit which executes the predetermined processing in response t
    Type: Application
    Filed: June 30, 2008
    Publication date: January 8, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Keita KOBAYASHI, Ryoko MORITA, Yusuke ITO, Naoya ICHINOSE, Shoichi ARAKI, Osamu NISHIMURA, Toshio SASAOKA, Yoko MATSUSHIMA
  • Publication number: 20080004782
    Abstract: A processing time necessary from start by end of processing of a first processing group and a second processing group is calculated. A time difference between a dead line previously set as a maximum tolerance value of the processing time necessary by completion of the processing of the first processing group, and the calculated processing time is calculated. An initial value of a processing time allowable value of the second processing group is calculated based on the time difference. The processing time allowable value is updated at the time of processing in the operating system. It is judged whether or not the second processing group can be executable based on the updated processing time allowable value.
    Type: Application
    Filed: May 14, 2007
    Publication date: January 3, 2008
    Inventors: Keita Kobayashi, Yusuke Ito, Naoya Ichinose, Youko Matsushima, Ryoko Morita, Toshio Sasaoka
  • Publication number: 20070266230
    Abstract: According to a generated instruction, the present invention provides an information processing method for performing processing by using a CPU that comprises at least one register. The method comprises the steps of: judging whether or not each of the registers is valid in the instruction; identifying a register whose value is changed by an interrupt processing generated in the instruction; and calculating a number of registers to be evacuated in the interrupt processing based on valid judgment information of the register and identification information of the register whose value is changed by the interrupt processing, and determining whether or not the interrupt processing is permitted based on a calculation result thereof.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 15, 2007
    Inventor: Naoya Ichinose