Abstract: A processing circuit according to an embodiment includes a plurality of logic gates in combination each of which is configured to probabilistically determine, based on signal values of one or two or more input nodes and output nodes at a certain time, signal values at at least one of the input nodes and the output nodes at a subsequent time, in which the processing circuit controls the signal values based on a relationship to be satisfied between at least some nodes of the input nodes and the output nodes.

Abstract: A random number generator according to one embodiment includes a write circuit, a read circuit, and a signal output circuit. The write circuit inverts magnetization of a magnetic layer of a magnetic tunnel junction element stochastically by supplying current to the magnetic layer. The read circuit reads the magnetization. The signal output circuit generates a random number on the basis of the magnetization read by the read circuit. The random number generator includes a sequence control circuit that controls the write circuit and the read circuit. The sequence control circuit regulates the write circuit to supply the current to the write circuit in a first period, and causes the read circuit to read the magnetization after the first period is finished and then a second period longer than the first period is elapsed.

Abstract: A random number generator according to one embodiment includes a write circuit, a read circuit, and a signal output circuit. The write circuit inverts magnetization of a magnetic layer of a magnetic tunnel junction element stochastically by supplying current to the magnetic layer. The read circuit reads the magnetization. The signal output circuit generates a random number on the basis of the magnetization read by the read circuit. The random number generator includes a sequence control circuit that controls the write circuit and the read circuit. The sequence control circuit regulates the write circuit to supply the current to the write circuit in a first period, and causes the read circuit to read the magnetization after the first period is finished and then a second period longer than the first period is elapsed.

Abstract: Internet routers are a key component in today's Internet. Each router forwards received packets toward their final destinations based upon a Longest Prefix Matching (LPM) algorithm select an entry from a routing table that determines the closest location to the final packet destination among several candidates. Prior art solutions to LPM lookup offer different tradeoffs and that it would be beneficial for a design methodology that provides for low power large scale IP lookup engines addressing the limitations within the prior art. According to embodiments of the invention a low-power large-scale IP lookup engine may be implemented exploiting clustered neural networks (CNNs). In addition to reduced power consumption embodiments of the invention provide reduced transistor count providing for reduced semiconductor die footprints and hence reduced die cost.

Abstract: Internet routers are a key component in today's Internet. Each router forwards received packets toward their final destinations based upon a Longest Prefix Matching (LPM) algorithm select an entry from a routing table that determines the closest location to the final packet destination among several candidates. Prior art solutions to LPM lookup offer different tradeoffs and that it would be beneficial for a design methodology that provides for low power large scale IP lookup engines addressing the limitations within the prior art. According to embodiments of the invention a low-power large-scale IP lookup engine may be implemented exploiting clustered neural networks (CNNs). In addition to reduced power consumption embodiments of the invention provide reduced transistor count providing for reduced semiconductor die footprints and hence reduced die cost.

Abstract: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.

Abstract: An asynchronous protocol converter, which is capable of flexibly carrying out communications between tens of IP cores in an asynchronous protocol Network-on-Chip system, and which is multiple input multiple output is provided. In an LSI (20), which comprises a plurality of IP cores (21), and routers (22) positioned adjacent to the plurality of IP cores (21), an asynchronous protocol converter (1) is positioned between adjacent routers (22). The asynchronous protocol converter (1) is configured to comprise: a two-to-four-phase converter (11) that is connected to an adjacent router (22a) within the LSI (20); a four-phase pipelined router (12) that is connected on the output side of the two-to-four-phase converter (11); a four-to-two-phase converter (13) that is connected to the outputs of the four-phase pipelined router (12); an input controller (14) that controls the two-to-four-phase converter (11); and an output controller (15) that controls the four-to-two-phase converter (13).

Abstract: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.

Abstract: Internet routers are a key component in today's Internet. Each router forwards received packets toward their final destinations based upon a Longest Prefix Matching (LPM) algorithm select an entry from a routing table that determines the closest location to the final packet destination among several candidates. Prior art solutions to LPM lookup offer different tradeoffs and that it would be beneficial for a design methodology that provides for low power large scale IP lookup engines addressing the limitations within the prior art. According to embodiments of the invention a low-power large-scale IP lookup engine may be implemented exploiting clustered neural networks (CNNs). In addition to reduced power consumption embodiments of the invention provide reduced transistor count providing for reduced semiconductor die footprints and hence reduced die cost.

Abstract: An asynchronous protocol converter, which is capable of flexibly carrying out communications between tens of IP cores in an asynchronous protocol Network-on-Chip system, and which is multiple input multiple output is provided. In an LSI (20), which comprises a plurality of IP cores (21), and routers (22) positioned adjacent to the plurality of IP cores (21), an asynchronous protocol converter (1) is positioned between adjacent routers (22). The asynchronous protocol converter (1) is configured to comprise: a two-to-four-phase converter (11) that is connected to an adjacent router (22a) within the LSI (20); a four-phase pipelined router (12) that is connected on the output side of the two-to-four-phase converter (11); a four-to-two-phase converter (13) that is connected to the outputs of the four-phase pipelined router (12); an input controller (14) that controls the two-to-four-phase converter (11); and an output controller (15) that controls the four-to-two-phase converter (13).