Abstract: An optical phase modulator includes a rib part extending in an extending direction. The rib part includes an N-type first rib portion and a P-type second rib portion arranged in a width direction to have a PN junction therebetween along the extending direction. An N-type first slab portion is connected to the first rib portion and a P-type second slab portion is connected to the second rib portion to provide a PN structure with the rib part in a cross-section having a normal direction along the extending direction. A P-type third slab portion is connected to the first rib portion and an N-type fourth slab portion is connected to the second rib portion to have a PNPN structure with the rib part in a cross-section having a normal direction along the extending direction. The PN structure and the PNPN structure are alternately disposed in the extending direction.

Abstract: A semiconductor device includes a semiconductor element, a substrate, and a plurality of wires. The semiconductor element has a plurality of electrodes on a first surface. The substrate has an element mount portion to which a second surface of the semiconductor element is joined through a solder joining material, a plurality of bonding portions disposed on a periphery of the element mount portion and spaced apart from each other, and a solder absorption portion extending outwardly from the element mount portion to receive a surplus of the solder joining material and being electrically independent of the plurality of bonding portions. The wires connect the electrodes and the bonding portions. The element mount portion and the solder absorption portion have a higher solder wettability than another portion of the substrate.

Abstract: Embodiments described herein generally relate to an electronics assembly that includes a semiconductor device, a substrate layer, a first mesh layer and a second mesh layer. Jet channels that have a first inner diameter are disposed within the substrate layer. The first mesh layer includes a first plurality of pores that have a perimeter opening. The second mesh layer includes a second plurality of pores that have a second inner diameter. The jet channels, the first and the second plurality of pores are concentric to create a fluid path for a fluid to impinge a first device surface of the semiconductor device. The second inner diameter is smaller than the perimeter opening and the first inner diameter of the substrate layer such that a cooling fluid velocity increases when flowing from the substrate layer through the second mesh layer.

Abstract: A power electronics module includes an electrically-conductive substrate including a base portion defining a plurality of orifices that extend through the base portion, the plurality of orifices defining a plurality of jet paths extending along and outward from the plurality of orifices, and a plurality of posts extending outward from the base portion, where individual posts of the plurality of posts are positioned between individual orifices of the plurality of orifices, and a power electronics device coupled to the plurality of posts opposite the base portion, the power electronics device defining a bottom surface that is oriented transverse to the plurality of jet paths.

Abstract: An assembly that includes a first substrate, a second substrate, and a pair of bonding layers disposed between and bonded to the first and second substrates. The assembly further includes a solder layer disposed between the pair of bonding layers such that the solder layer is isolated from contacting the first substrate and the second substrate. The solder layer has a low melting temperature relative to a high melting temperature of the bonding layers. A coating is disposed over at least the pair of bonding layers and the solder layer such that the coating encapsulates the solder layer between the pair of bonding layers. The solder layer melts into a liquid form when the assembly operates at a temperature above the low melting temperature of the solder layer and the coating maintains the liquid form of the solder layer between the pair of bonding layers.

Abstract: A power electronics module includes a power electronics device, and an electrically-conductive substrate directly coupled to the power electronics device, the electrically-conductive substrate defining a plurality of channels extending through the electrically-conductive substrate, and a plurality of electrical pathways extending through the electrically-conductive substrate around the plurality of channels.

Abstract: Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.

Abstract: Embodiments of the present disclosure include a method of forming an electronic assembly with a mesh bond layer. The method may include forming a mesh bond material comprising a first surface spaced apart from a second surface by a thickness of the mesh bond material and one or more openings extending from the first surface through the thickness of the mesh bond material to the second surface. The method may further include adjusting at least one of: the thickness of the mesh bond material, a geometry of the one or more openings, or a size of the one or more openings of the mesh bond material, where the adjusting modifies a Young's modulus of the mesh bond material, and bonding the first surface of the mesh bond material to a surface of a semiconductor device.

Abstract: A self-healing metal structure is provided for transferring heat between an electronics component and a substrate. The self-healing metal structure includes a base metal structural component. A phase change material is provided adjacent at least a portion of the base metal structural component. A protective component at least partially encapsulates the phase change material. Upon the presence of a spatial defect in the base metal structural component, the phase change material reacts with the base structural component to form an intermetallic compound to at least partially occupy the spatial defect. The phase change material at least partially encapsulated with the protective component may be disposed within the base metal structural component as a plurality of separate capsules incorporated therein, or the phase change material at least partially surrounds the base metal structural component.

Abstract: Methods for forming bonded assemblies using metal inverse opal and cap structures are disclosed. In one embodiment, a method for forming a bonded assembly includes positioning a substrate against a polymer support that is porous, depositing a metal onto and within the polymer support, disposing a cap layer to the polymer support opposite of the substrate to form a bottom electrode, and removing the polymer support from between the substrate and the cap layer to form a metal inverse opal structure disposed therebetween.

Abstract: An assembly that includes a first substrate, a second substrate, and a stress mitigation layer disposed between the first and the second substrates. The stress mitigation layer is directly bonded onto the second substrate, and the second substrate is separated from the intermetallic compound layer by the stress mitigation layer. The stress mitigation layer has a high purity of at least 99% aluminum such that the stress mitigation layer reduces thermomechanical stresses on the first and second substrates. The assembly further includes an intermetallic compound layer disposed between the first substrate and the stress mitigation layer such that the stress mitigation layer is separated from the first substrate by the intermetallic compound layer.

Abstract: Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.

Abstract: An assembly includes a substrate including a base portion defining a plurality of orifices that extend through the base portion, the plurality of orifices defining a plurality of jet paths extending along and outward from the plurality of orifices, a mesh coupled to the base portion, the mesh defining a plurality of pores aligned with the plurality of jet paths, and a heat-generating device coupled to the mesh opposite the base portion, the heat-generating device defining a bottom surface that is oriented transverse to the plurality of jet paths.

Abstract: The present disclosure generally relates to a stack including cooling tubes embedded within a solder, and methods of forming the same. A method of forming a stack includes placing a first amount of bond layer precursor material on a substrate, placing one or more cooling tubes on the first amount of bond layer precursor material, the one or more cooling tubes having a ceramic tube wall electroplated with a metal, placing a second amount of bond layer precursor material on the one or more cooling tubes such that the one or more cooling tubes are surrounded by bond layer precursor material placing an assembly having the one or more heat generating devices on the second amount of bond layer precursor material, and performing a bonding process to form a bond layer between the assembly and the substrate with the one or more cooling tubes disposed in the bond layer.

Abstract: A semiconductor device may include a semiconductor element including a signal pad, an encapsulant encapsulating the semiconductor element and a lead including a first end located outside the encapsulant and a second end located within the encapsulant. The lead may be connected to the signal pad via a bonding wire within the encapsulant. The lead may include an upper surface extending from the first end to the second end. The upper surface may include a joined section where the bonding wire is joined and a rough section located within the encapsulant and having a higher surface roughness than the joined section. The rough section may be at least partly located lower than the joined section.

Abstract: Methods for forming bonded assemblies using metal inverse opal and cap structures are disclosed. In one embodiment, a method for forming a bonded assembly includes positioning a substrate against a polymer support that is porous, depositing a metal onto and within the polymer support, disposing a cap layer to the polymer support opposite of the substrate to form a bottom electrode, and removing the polymer support from between the substrate and the cap layer to form a metal inverse opal structure disposed therebetween.

Abstract: Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.

Abstract: An assembly includes a substrate including a base portion defining a plurality of orifices that extend through the base portion, the plurality of orifices defining a plurality of jet paths extending along and outward from the plurality of orifices, a mesh coupled to the base portion, the mesh defining a plurality of pores aligned with the plurality of jet paths, and a heat-generating device coupled to the mesh opposite the base portion, the heat-generating device defining a bottom surface that is oriented transverse to the plurality of jet paths.

Abstract: Embodiments described herein generally relate to an electronics assembly that includes a semiconductor device, a substrate layer, a first mesh layer and a second mesh layer. Jet channels that have a first inner diameter are disposed within the substrate layer. The first mesh layer includes a first plurality of pores that have a perimeter opening. The second mesh layer includes a second plurality of pores that have a second inner diameter. The jet channels, the first and the second plurality of pores are concentric to create a fluid path for a fluid to impinge a first device surface of the semiconductor device. The second inner diameter is smaller than the perimeter opening and the first inner diameter of the substrate layer such that a cooling fluid velocity increases when flowing from the substrate layer through the second mesh layer.

Abstract: A power electronics module includes a power electronics device, and an electrically-conductive substrate directly coupled to the power electronics device, the electrically-conductive substrate defining a plurality of channels extending through the electrically-conductive substrate, and a plurality of electrical pathways extending through the electrically-conductive substrate around the plurality of channels.