Abstract: A differential communication circuit includes: a first switch in between a signal line and a power source, a second switch in between a signal line and a ground, a third switch in between the signal line and the ground, a fourth switch in between the signal line and the power source, first and second drivers respectively driving the first and second switches, and third and fourth drivers respectively driving the third and fourth switches OFF to ON at an ON to OFF timing of the first and second switches, for setting an ON period of the third and fourth switches to be shorter than a one-bit width in a communication signal and enabling a stable signal level determination while reducing power consumption of the differential communication circuit.

Abstract: A differential communication circuit includes: a first switch in between a signal line and a power source, a second switch in between a signal line and a ground, a third switch in between the signal line and the ground, a fourth switch in between the signal line and the power source, first and second drivers respectively driving the first and second switches, and third and fourth drivers respectively driving the third and fourth switches OFF to ON at an ON to OFF timing of the first and second switches, for setting an ON period of the third and fourth switches to be shorter than a one-bit width in a communication signal and enabling a stable signal level determination while reducing power consumption of the differential communication circuit.

Abstract: A signal input circuit includes: a signal input device having a signal input terminal; an inspection capacitor connected between the signal input terminal and a reference potential; a connection unit connecting/disconnecting an inspection path between the inspection capacitor and the signal input terminal; a charge and discharge unit charging/discharging the inspection capacitor; and a determination processing unit carrying out a terminal failure detection processing. The determination processing unit controls the connection unit to disconnect the inspection path and controls the charge and discharge unit to set the voltage of the inspection capacitor to a terminal inspection voltage in a charge and discharge procedure, controls the connection unit to connect the inspection path in a continuity establishing procedure, and detects the terminal failure at the signal input terminal or a communication path from the signal input terminal based on a voltage of the inspection path.

Abstract: A control apparatus including a non-volatile RAM divided into a plurality of memory regions including ROM region and RAM region, CPU capable of executing a plurality of types of access to the non-volatile RAM and a protecting portion intervening between the CPU and the non-volatile RAM. The protecting portion includes a register for storing address information capable of specifying address ranges corresponding to the ROM region and RAM region among the memory regions of the non-volatile RAM, access enabling module for enabling the CPU to write data to the ROM region while an enable signal inputted to the protecting portion externally is active, when the CPU performs a write-access to the ROM region, and initializing module for initializing the address information stored in the register to be predetermined address information as an initial value when the enable signal is deactivated after activating the enable signal.

Abstract: A signal input circuit includes: a signal input device having a signal input terminal; an inspection capacitor connected between the signal input terminal and a reference potential; a connection unit connecting/disconnecting an inspection path between the inspection capacitor and the signal input terminal; a charge and discharge unit charging/discharging the inspection capacitor; and a determination processing unit carrying out a terminal failure detection processing. The determination processing unit controls the connection unit to disconnect the inspection path and controls the charge and discharge unit to set the voltage of the inspection capacitor to a terminal inspection voltage in a charge and discharge procedure, controls the connection unit to connect the inspection path in a continuity establishing procedure, and detects the terminal failure at the signal input terminal or a communication path from the signal input terminal based on a voltage of the inspection path.

Abstract: A control apparatus including a non-volatile RAM divided into a plurality of memory regions including ROM region and RAM region, CPU capable of executing a plurality of types of access to the non-volatile RAM and a protecting portion intervening between the CPU and the non-volatile RAM. The protecting portion includes a register for storing address information capable of specifying address ranges corresponding to the ROM region and RAM region among the memory regions of the non-volatile RAM, access enabling means for enabling the CPU to write data to the ROM region while an enable signal inputted to the protecting portion externally is active, when the CPU performs a write-access to the ROM region, and initializing for initializing the address information stored in the register to be predetermined access information as an initial value when the enable signal is deactivated after activating the enable signal.

Abstract: In order to drive an L load, FETs are disposed so as to be mirror-paired with FETs disposed at the power source side and the ground side respectively, and currents corresponding to mirrored currents of first and second currents flowing in FETs are made to flow in current mirror circuits, and the mirror ratio of the former is set so that the current ratio of the first current ratio is large, and the mirror ratio of the latter is set so that the current ratio of the second current side is large. When the first current is larger than the second current, the current flowing in the transistor through the mirror circuit is increased to set the transistor to a conducting state, and when the second current is larger than the first current, the current flowing in the transistor through the mirror circuit is increased to set the transistor to a conducting state.

Abstract: A load drive apparatus includes a drive signal control circuit for generating multiple drive signals, each of which is provided to each of the loads. The drive signal control circuit changes a phase of the drive signals in accordance with the number of the loads to equalize a phase difference between each of the drive signals. Therefore, it is less likely that all the loads are simultaneously driven. A concentrated increase in a load current can be prevented so that an increase in peak values of noise and heat production can be prevented.

Abstract: In a circuit according to the present invention, a multi-collector transistor is provided which includes first to third collectors so that, when a current does not flow from the second collector, a current from the first collector increases but a current from the third collector does not vary. When transistors of the circuit turn off because the voltage of an input signal gets out of an in-phase input voltage range, the supply of the current from the second collector comes to a stop and, hence, the current from the first collector increases. In this situation, further transistors carry out their on/off operations, thereby fixing the output of the circuit to a low level. That is, this circuit can, irrespective of poor pair compatibility between the transistors, fix the output logical level to a desired level when the voltage of an input signal gets out of an in-phase input voltage range.

Abstract: In order to drive an L load, FETs are disposed so as to be mirror-paired with FETs disposed at the power source side and the ground side respectively, and currents corresponding to mirrored currents of first and second currents flowing in FETs are made to flow in current mirror circuits, and the mirror ratio of the former is set so that the current ratio of the first current ratio is large, and the mirror ratio of the latter is set so that the current ratio of the second current side is large. When the first current is larger than the second current, the current flowing in the transistor through the mirror circuit is increased to set the transistor to a conducting state, and when the second current is larger than the first current, the current flowing in the transistor through the mirror circuit is increased to set the transistor to a conducting state.

Abstract: In a circuit according to the present invention, a multi-collector transistor is provided which includes first to third collectors so that, when a current does not flow from the second collector, a current from the first collector increases but a current from the third collector does not vary. When transistors of the circuit turn off because the voltage of an input signal gets out of an in-phase input voltage range, the supply of the current from the second collector comes to a stop and, hence, the current from the first collector increases. In this situation, further transistors carry out their on/off operations, thereby fixing the output of the circuit to a low level. That is, this circuit can, irrespective of poor pair compatibility between the transistors, fix the output logical level to a desired level when the voltage of an input signal gets out of an in-phase input voltage range.