Abstract: A transistor having a trench gate is controlled such that values settable as on current of the transistor are not discrete. A first transistor includes a plurality of first trenches, a first gate insulating film, and a first gate electrode. The first trenches are provided on a substrate, and are arranged side by side in a plan view. The first gate insulating film is provided on at least a side face of each of the first trenches, and over each of substrate regions located between the first trenches. The first gate electrode is embedded in each of the first trenches, and is provided over each of regions of the first gate insulating film located between the first trenches. At least one of the first trenches is formed as a circular trench in a plan view.

Abstract: A design method of a semiconductor device includes setting an inspection region of layout data generated based on circuit data, calculating an area ratio of a first area to a second area, the first area indicating an area of the inspection region, the second area indicating a sum of a surface area of a plane that a first member contacts with a second member, the second member contacting with the first member constituting a circuit element included in the inspection region, the second member further having different heat reflective properties from the first member, and arranging a dummy element in the layout data so that the area ratio is within a predetermined range in each inspection region of the layout data.

Abstract: When a metal cap film is provided on an electric fuse, the break-ability of the electric fuse is reduced. A semiconductor device 1 includes interconnects 10, an electric fuse 20 and metal cap films 30. Both of the interconnects 10 and the electric fuse 20 are composed of Cu. The interconnects 10 and the electric fuse 20 are provided in the same layer in the interconnect layer 40. The metal cap films 30 are provided only on the interconnects 10 and not provided on the electric fuse 20.

Abstract: When a metal cap film is provided on an electric fuse, the break-ability of the electric fuse is reduced. A semiconductor device 1 includes interconnects 10, an electric fuse 20 and metal cap films 30. Both of the interconnects 10 and the electric fuse 20 are composed of Cu. The interconnects 10 and the electric fuse 20 are provided in the same layer in the interconnect layer 40. The metal cap films 30 are provided only on the interconnects 10 and not provided on the electric fuse 20.

Abstract: A design method of a semiconductor device includes setting an inspection region of layout data generated based on circuit data, calculating an area ratio of a first area to a second area, the first area indicating an area of the inspection region, the second area indicating a sum of a surface area of a plane that a first member contacts with a second member, the second member contacting with the first member constituting a circuit element included in the inspection region, the second member further having different heat reflective properties from the first member, and arranging a dummy element in the layout data so that the area ratio is within a predetermined range in each inspection region of the layout data.

Abstract: A semiconductor device includes an insulating interlayer formed above a silicon substrate and provided with a concave portion in a certain location, a barrier metal film covering an inner wall of the insulating interlayer, a lower layer copper interconnect provided so as to be in contact with the barrier metal film and buried in the interior of the concave portion, and a protective film provided so as to be in contact with the lower layer copper interconnect and also provided on substantially the entire top surface of the lower layer copper interconnect. An upper surface of the lower layer copper interconnect is provided so as to be retracted to be closer to the substrate than an upper surface of barrier metal film on the side wall of the concave portion.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Abstract: In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such that the trench is filled in with the metal layer; (D) forming the interconnection by removing an excess metal layer outside the trench; (E) modifying a surface of the insulating film to form a modified layer on the insulating film; and (F) forming a metal film selectively on the interconnection by using plating solution after the (E) modifying process.

Abstract: A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.

Abstract: A semiconductor device includes an insulating interlayer formed above a silicon substrate and provided with a concave portion in a certain location, a barrier metal film covering an inner wall of the insulating interlayer, a lower layer copper interconnect provided so as to be in contact with the barrier metal film and buried in the interior of the concave portion, and a protective film provided so as to be in contact with the lower layer copper interconnect and also provided on substantially the entire top surface of the lower layer copper interconnect. An upper surface of the lower layer copper interconnect is provided so as to be retracted to be closer to the substrate than an upper surface of barrier metal film on the side wall of the concave portion.

Abstract: In a semiconductor integrated circuit device, a sheet-like temperature monitor member of vanadium oxide is provided, whose one end is connected to one via while the other end is connected to another via. A sheet-like thermal conducting layer of aluminum is provided below the temperature monitor member. A region equal to or greater than a half of the entire temperature monitor member overlies the thermal conducting layer in a plan view.

Abstract: When a metal cap film is provided on an electric fuse, the break-ability of the electric fuse is reduced. A semiconductor device 1 includes interconnects 10, an electric fuse 20 and metal cap films 30. Both of the interconnects 10 and the electric fuse 20 are composed of Cu. The interconnects 10 and the electric fuse 20 are provided in the same layer in the interconnect layer 40. The metal cap films 30 are provided only on the interconnects 10 and not provided on the electric fuse 20.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such that the trench is filled in with the metal layer; (D) forming the interconnection by removing an excess metal layer outside the trench; (E) modifying a surface of the insulating film to form a modified layer on the insulating film; and (F) forming a metal film selectively on the interconnection by using plating solution after the (E) modifying process.

Abstract: A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.

Abstract: In a semiconductor integrated circuit device, a sheet-like temperature monitor member of vanadium oxide is provided, whose one end is connected to one via while the other end is connected to another via. A sheet-like thermal conducting layer of aluminum is provided below the temperature monitor member. A region equal to or greater than a half of the entire temperature monitor member overlies the thermal conducting layer in a plan view.

Abstract: In a semiconductor integrated circuit device, a logic circuit section is provided at the top surface of a P-type silicon substrate and a multi-level wiring layer. The device is further provided with a temperature sensor section in which a first temperature monitor member of vanadium oxide is provided above the multi-level wiring layer. A second temperature monitor member of Ti is provided at a lowermost layer of the multi-level wiring layer. The first and second temperature monitor members are connected in series between a ground potential wire and a power-source potential wire, with an output terminal connected to the node of both members. The temperature coefficient of the electric resistivity of the first temperature monitor member is negative, while that of the second temperature monitor member is positive.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, wires of the topmost wiring layer of a multi-layer wiring structure are formed. A sheet-like temperature monitor element of vanadium oxide is provided between two of the wires in such a way as to cover the two wires. Accordingly, the temperature monitor element is connected between the two wires of an underlying wiring layer of the multi-layer wiring structure through two vias and the two wires of the topmost wiring layer.

Abstract: In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer is provided in such a way as to cover the multi-layer wiring layer and the pads, second vias are so formed as to reach the pads. Vanadium oxide is buried in the second vias by reactive sputtering, and a temperature monitor part of vanadium oxide is provided in such a way as to connect the second vias each other. Accordingly, the temperature monitor part is connected between the two wires.