Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed.

Abstract: In a semiconductor device having a thin SOI film, the thickness of a semiconductor layer formed on an insulating film is so adjusted as to be less than a maximum distance allowable to complete depletion of the layer. While the thickness of a channel region is adjusted to be less than that of impurity-diffusion regions. Further, the insulating layer is so formed to have a thicker portion under the channel region, and thinner portions under the source region and the drain region as the impurity-diffusion regions. The semiconductor layer has steps at the boundaries between the channel region and the impurity-diffusion regions, and the top face of the channel region is arranged so as to be lower than the top faces of the impurity-diffusion regions. A region having a width less than the maximum depletion distance and an impurity concentration larger, than that of the channel region and less than that of the drain region is formed between the channel region and the drain region.

Abstract: A semiconductor memory device, in particular a dynamic random access memory cell which realizes a high speed thereof and presenting a superior controllability. The dynamic random access memory (DRAM) cell includes: a first transistor; a second transistor, electrically connected in series to the first transistor, for storing an electric charge, the second transistor including a portion for erasing the charge stored at the second transistor, wherein the first transistor and the second transistor are electrically connected between a power line and a bit line; and a diode electrically connected between the first transistor and the second transistor.

Abstract: A MOSFET comprises a silicon substrate 1 having a source/drain region 7b formed in a surface region thereof, an insulating film 3 formed of silicon oxide, and a gate electrode 4a. The side surface region of the electrode 4a is covered with an insulating film 6 formed of silicon nitride. The insulating film 6 has an extended portion interposed between the electrode 4a and the insulating film 3 in a manner to surround the lower corner portion 4b of the electrode. Since the insulating film 6 has a dielectric constant larger than that of the insulating film 3, it is possible to suppress the electric field intensity at the lower corner portion 4b of the electrode.

Abstract: A triangular mesh generation apparatus has a feedback rate calculation unit and a triangular mesh generation unit. The feedback rate calculation unit obtains feedback rate r.sub.i for a given node i from the following relationship: ##EQU1## where d.sub.i is a distance between the respective adjacent nodes, a is a distance between nodes i-1 and i, b is a distance between nodes i and i+1, and .alpha.>0. The triangular ratio generation unit generates triangular meshes as follows:(1) When .theta..ltoreq.90.degree., a triangular element is generated by node i and its adjacent nodes i-1 and i+1.(2) When 90.degree.<.theta.<150.degree., node j1' is obtained on a line dividing internal boundary angle .theta. into two equal parts at distance l1'=r.sub.i .times.l1 from node i. Then, two triangular elements are respectively generated by nodes i, i-1, and j1', and nodes i, i+1, and j1'. Here, l1= ##EQU2## (3) When 150.degree.<.theta.<180.degree.

Abstract: A method of manufacturing a MOS device wherein a semiconductor substrate is selectively etched to form a groove in a field region and an element formation region surrounded by the groove such that an angle .theta. is formed between a wall of the groove and a first imaginary extension of a top surface of the element formation region, the angle .theta. satisfying the relation, 70.degree..ltoreq..theta..ltoreq.90.degree.. Then, a field insulating film is deposited in the groove, and a MOS transistor is formed in the element formation region. The element formation region has source, drain and channel regions of a field effect transistor therein and a gate electrode formed on a gate insulating film on the channel region. The gate electrode extends onto the surface portion of the field insulating film.

Abstract: A voltage-control type semiconductor switching device is disclosed which includes a pair of controlled electrodes to which a control voltage signal is supplied, and a semiconductive layer formed between the electrodes so as electrically insulative from the electrodes through insulative layers. The semiconductive layer has a channel region and a carrier-storage region which is substantially nonconductive. The channel region is formed laterally along the longitudinal direction of the electrodes, thereby allowing majority carriers such as electrons of the semiconductive layer to flow in the lateral direction. In the current cut-off mode, the carrier-storage region temporarily stores the carriers which move in the direction of thickness of the semiconductive layer due to the electric field created by the voltage. In the current conduction mode, the carrier-storage region releases the carriers stored therein toward the channel region.