Patents by Inventor Naoyuki Tsuda

Naoyuki Tsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953786
    Abstract: A lens portion of a display device includes: a first lens arranged between a light guide plate and a light-emitting element portion, and having a plurality of first prisms arranged on a first light-exiting surface; and a second lens arranged between the first lens and the light-emitting element portion, and having a plurality of second prisms arranged on a second light-exiting surface arranged at a position facing a light-entering surface. The first lens includes a plurality of diffusing prisms arranged on the light-entering surface and capable of diffusing light emitted from the second lens and introducing said light into the first lens.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: April 9, 2024
    Assignee: Japan Display Inc.
    Inventors: Motoki Tsuda, Naoyuki Asano, Kazuki Ichihara
  • Publication number: 20240085731
    Abstract: A display device includes a display panel including a polymer-dispersed liquid crystal layer between a pair of substrates, a transparent substrate disposed on at least one side of the display panel, and a lighting unit configured to project light from the side of the transparent substrate. The lighting unit includes at least one light source, at least one light guide incident with the light emitted from the light source, and a support member having an L-shaped cross section and extending along one side of the display panel to which the at least one light source and the at least one light guide are fixed. The at least one light source and the at least one light guide are disposed on different sides of the support member. The lighting unit is fixed to the transparent substrate or the display panel by the support member.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Kazuki ICHIHARA, Naoyuki ASANO, Motoki TSUDA
  • Publication number: 20240069388
    Abstract: A lens portion of a display device includes: a first lens arranged between a light guide plate and a light-emitting element portion, and having a plurality of first prisms arranged on a first light-exiting surface; and a second lens arranged between the first lens and the light-emitting element portion, and having a plurality of second prisms arranged on a second light-exiting surface arranged at a position facing a light-entering surface. The first lens includes a plurality of diffusing prisms arranged on the light-entering surface and capable of diffusing light emitted from the second lens and introducing said light into the first lens.
    Type: Application
    Filed: August 21, 2023
    Publication date: February 29, 2024
    Inventors: Motoki TSUDA, Naoyuki ASANO, Kazuki ICHIHARA
  • Patent number: 7687015
    Abstract: A method for producing a laminated dielectric, which comprises laminating a raw material layer containing a high dielectric constant glass ceramic composition comprising from 30 to 70 mass % of a Ba—Ti compound powder having a Ti/Ba molar ratio of from 3.0 to 5.7 and from 30 to 70 mass % of an alkali free glass powder containing, by mol %, from 15 to 40% of SiO2, from 5 to 37% of B2O3, from 2 to 15% of Al2O3, from 1 to 25% of CaO+SrO, from 5 to 25% of BaO and from 25 to 50% of SiO2+Al2O3, and a raw material layer containing a low dielectric constant glass ceramic composition comprising from 10 to 70 mass % of a ceramic powder and from 30 to 90 mass % of an alkali free glass powder wherein SiO2+Al2O3 is at least 34 mol % and larger by at least 9 mol % than that in the above alkali free glass powder, followed by firing.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: March 30, 2010
    Assignee: Asahi Glass Company, Limited
    Inventors: Shotaro Watanabe, Yasuko Osaki, Naoyuki Tsuda, Kazunari Watanabe
  • Publication number: 20060075782
    Abstract: A method for producing a laminated dielectric, which comprises laminating a raw material layer containing a high dielectric constant glass ceramic composition comprising from 30 to 70 mass % of a Ba—Ti compound powder having a Ti/Ba molar ratio of from 3.0 to 5.7 and from 30 to 70 mass % of an alkali free glass powder containing, by mol %, from 15 to 40% of SiO2, from 5 to 37% of B2O3, from 2 to 15% of Al2O3, from 1 to 25% of CaO+SrO, from 5 to 25% of BaO and from 25 to 50% of SiO2+Al2O3, and a raw material layer containing a low dielectric constant glass ceramic composition comprising from 10 to 70 mass % of a ceramic powder and from 30 to 90 mass % of an alkali free glass powder wherein SiO2+Al2O3 is at least 34 mol % and larger by at least 9 mol % than that in the above alkali free glass powder, followed by firing.
    Type: Application
    Filed: November 21, 2005
    Publication date: April 13, 2006
    Applicant: Asahi Glass Company, Limited
    Inventors: Shotaro Watanabe, Yasuko Osaki, Naoyuki Tsuda, Kazunari Watanabe
  • Patent number: 5170237
    Abstract: A semiconductor pressure sensor comprising a diaphragm area formed on a semiconductor chip, a plurality of gauge resistances arranged on one face of the diaphragm area to form a bridge circuit, and an oxide film formed on the top of the diaphragm area, wherein at least one additional pattern is formed in a portion of said diaphragm area other than said gauge resistances. The thickness of the oxide film on said additional pattern is smaller than the thickness of the oxide film on portions other than said gauge resistances and said additional pattern.
    Type: Grant
    Filed: November 2, 1990
    Date of Patent: December 8, 1992
    Assignee: Matsushita Electronics Corporation
    Inventors: Naoyuki Tsuda, Tsuneo Yamaguchi, Tadataka Kaneko
  • Patent number: 4064525
    Abstract: A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the abovementioned way, respectively, of the other FET. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage.
    Type: Grant
    Filed: June 15, 1976
    Date of Patent: December 20, 1977
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Gota Kano, Naoyuki Tsuda, Hitoo Iwasa