Abstract: A very high speed cyclic redundancy code (CRC) generator/tester used to implement a CRC polynomial for purposes of detecting errors in telecommunications data. A given n-bit word message to be transmitted over some medium is first processed by the very high speed CRC generator/tester in order to generate, in parallel format, a cyclic redundancey code word to be attached to the message. The n-bit word message plus cyclic redundancy code word is then processed, in a manner identical to processing at the transmitter, at the receiver in order to establish if a transmission error has occurred. The parallel processing offered by this very high speed CRC generator/tester allows for much greater processing speeds than the prior art.