Patents by Inventor Narasimha R. Adiga
Narasimha R. Adiga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11163661Abstract: Test case generation for a hardware state space including: identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.Type: GrantFiled: August 9, 2019Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Madhusudan Kadiyala, Narasimha R. Adiga, Manoj Dusanapudi
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Publication number: 20210042202Abstract: Test case generation for a hardware state space including: identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.Type: ApplicationFiled: August 9, 2019Publication date: February 11, 2021Inventors: MADHUSUDAN KADIYALA, NARASIMHA R. ADIGA, MANOJ DUSANAPUDI
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Patent number: 9934041Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: GrantFiled: July 1, 2015Date of Patent: April 3, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
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Patent number: 9760462Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: GrantFiled: September 30, 2014Date of Patent: September 12, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
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Patent number: 9733946Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: GrantFiled: December 9, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
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Patent number: 9697001Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: GrantFiled: October 6, 2016Date of Patent: July 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Patent number: 9690587Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: GrantFiled: April 8, 2014Date of Patent: June 27, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Publication number: 20170083342Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: ApplicationFiled: December 9, 2016Publication date: March 23, 2017Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
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Publication number: 20170017493Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: ApplicationFiled: October 6, 2016Publication date: January 19, 2017Inventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Patent number: 9547495Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: GrantFiled: March 30, 2016Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
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Publication number: 20170003970Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: ApplicationFiled: July 1, 2015Publication date: January 5, 2017Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
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Publication number: 20170003968Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: ApplicationFiled: March 30, 2016Publication date: January 5, 2017Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
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Patent number: 9513909Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: GrantFiled: March 18, 2016Date of Patent: December 6, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Publication number: 20160188339Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: ApplicationFiled: March 18, 2016Publication date: June 30, 2016Inventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Patent number: 9304883Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: GrantFiled: April 25, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
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Publication number: 20150309904Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: International Business Machines CorporationInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
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Publication number: 20150309905Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: ApplicationFiled: September 30, 2014Publication date: October 29, 2015Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
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Publication number: 20150286483Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.Type: ApplicationFiled: April 8, 2014Publication date: October 8, 2015Applicant: International Business Machines CorporationInventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
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Patent number: 8693615Abstract: Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.Type: GrantFiled: December 17, 2012Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Narasimha R. Adiga, Peter H. Hochschild, Ashutosh Misra
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Patent number: 8345816Abstract: Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.Type: GrantFiled: December 6, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Narasimha R. Adiga, Peter H. Hochschild, Ashutosh Misra