Abstract: Certain aspects of the present disclosure provide techniques for communicating a user equipment (UE)'s capabilities to a network entity, such as a base station. An example method that may be performed by a UE includes transmitting a first message to a network entity, the first message comprising a base identification and a delta flag, wherein the base identification identifies base capabilities of the UE, and wherein the delta flag indicates whether there is delta information to be shared by the UE, the delta information corresponding to changes to the base capabilities of the UE. The method further includes determining whether to transmit a third message to the network entity based on whether the UE receives a second message from the network entity, the second message comprising a full capability flag indicating whether the UE should send an indication of its full capabilities to the network entity.

Abstract: Certain aspects of the present disclosure provide techniques for communicating a user equipment (UE)'s capabilities to a network entity, such as a base station. An example method that may be performed by a UE includes transmitting a first message to a network entity, the first message comprising a base identification and a delta flag, wherein the base identification identifies base capabilities of the UE, and wherein the delta flag indicates whether there is delta information to be shared by the UE, the delta information corresponding to changes to the base capabilities of the UE. The method further includes determining whether to transmit a third message to the network entity based on whether the UE receives a second message from the network entity, the second message comprising a full capability flag indicating whether the UE should send an indication of its full capabilities to the network entity.

Abstract: An enhanced Public Warning System (PWS) is provided. A User Equipment (UE) transmits a first indication of UE capability for performing a first set of UE actions. The UE receives based on the first indication, a second indication of a second set of UE actions the UE is to perform in response to receiving a warning message, the warning message including an identifier of a warning type associated with the second set of UE actions. The UE receives the warning message including the identifier of the warning type. The UE performs at least one of the second set of UE actions in response to receiving the warning message.

Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.

Abstract: An enhanced Public Warning System (PWS) is provided. A User Equipment (UE) transmits a first indication of UE capability for performing a first set of UE actions. The UE receives based on the first indication, a second indication of a second set of UE actions the UE is to perform in response to receiving a warning message, the warning message including an identifier of a warning type associated with the second set of UE actions. The UE receives the warning message including the identifier of the warning type. The UE performs at least one of the second set of UE actions in response to receiving the warning message.

Abstract: A method, an apparatus, a base station, and a computer-readable medium for wireless communication are provided. In some aspects, the apparatus may configure a wireless communication device to perform a measurement associated with a particular physical cell identifier (PCI) during a particular time period, wherein the apparatus is associated with the particular PCI. In some aspects, the apparatus may configure the apparatus not to transmit during the particular time period. In some aspects, the apparatus may determine whether the wireless communication device is associated with a PCI collision based at least in part on the measurement.

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.

Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.