Patents by Inventor Narasimhan Vijay Anand

Narasimhan Vijay Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11877237
    Abstract: The present invention provides a system and method for optimizing power consumption in Multimedia Signal Processing in mobile devices. The system comprises a Media (speech, audio, image, and video) codec encoder module, a Media codec decoder module (106) and pre-processing and postprocessing (filtering, deblocking filter, Analytics, person detect, keyword/keyframe spotting) modules modules. The pre-processing and post-processing modules are implemented on a DSPNLIW processor, while the Media encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipeline (asynchronous RPC, non-blocking) implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a multiple CPU/DSP/VLIW core with synchronous RPC (blocking). The significant reduction in current consumption of the modules enables reduction of power consumption in the Multimedia processing use case.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: January 16, 2024
    Assignee: TriSpace Technologies (OPC) Pvt. Ltd.
    Inventor: Narasimhan Vijay Anand
  • Publication number: 20230376649
    Abstract: The present invention provides a system and method for optimizing BoM cost of platform SoC in mobile devices. The system (100) comprises a CPU with SIMD extensions wherein video codec encoder/decoder module is implemented (101), and another CPU with SIMD extensions instead of DSP/VLIW core wherein post-processing filtering module (Deblocking filter) (102) module is implemented. Replacing DSP/VLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed is either case (deblocking filter on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.
    Type: Application
    Filed: February 23, 2023
    Publication date: November 23, 2023
    Inventor: Narasimhan Vijay Anand
  • Patent number: 11388670
    Abstract: The present invention provides a system and method for optimizing power consumption in voice communication in mobile devices. The system comprises pre-processing modules, a speech codec encoder module, a speech codec decoder module and post-processing modules. The pre-processing and post-processing modules are implemented on a DSP/VLIW processor, while the speech encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the talk time.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: July 12, 2022
    Assignee: TriSpace Technologies (OPC) Pvt. Ltd.
    Inventor: Narasimhan Vijay Anand
  • Patent number: 11330526
    Abstract: The present invention provides a system and method for optimizing power consumption in video communication in mobile devices. The system comprises a video codec encoder module, a video codec decoder module and post-processing filtering module (Deblocking filter) modules. The post-processing modules are implemented on a DSP/VLIW processor, while the video encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single/multiple DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the video call time. Thus, the invention provides a simple method of optimizing power consumption by multi core implementation of the modules in a video call in mobile devices.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 10, 2022
    Assignee: TriSpace Technologies (OPC) Pvt. Ltd.
    Inventor: Narasimhan Vijay Anand
  • Publication number: 20210392577
    Abstract: The present invention provides a system and method for optimizing power consumption in Multimedia Signal Processing in mobile devices. The system comprises a Media (speech, audio, image, and video) codec encoder module, a Media codec decoder module (106) and pre-processing and postprocessing (filtering, deblocking filter, Analytics, person detect, keyword/keyframe spotting) modules modules. The pre-processing and post-processing modules are implemented on a DSPNLIW processor, while the Media encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipeline (asynchronous RPC, non-blocking) implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a multiple CPU/DSP/VLIW core with synchronous RPC (blocking). The significant reduction in current consumption of the modules enables reduction of power consumption in the Multimedia processing use case.
    Type: Application
    Filed: June 7, 2021
    Publication date: December 16, 2021
    Inventor: Narasimhan Vijay Anand
  • Publication number: 20210377868
    Abstract: The present invention provides a system and method for optimizing power consumption in video communication in mobile devices. The system comprises a video codec encoder module, a video codec decoder module and post-processing filtering module (Deblocking filter) modules. The post-processing modules are implemented on a DSP/VLIW processor, while the video encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single/multiple DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the video call time. Thus, the invention provides a simple method of optimizing power consumption by multi core implementation of the modules in a video call in mobile devices.
    Type: Application
    Filed: December 21, 2020
    Publication date: December 2, 2021
    Inventor: Narasimhan Vijay Anand
  • Publication number: 20210084592
    Abstract: The present invention provides a system and method for optimizing power consumption in voice communication in mobile devices. The system comprises pre-processing modules, a speech codec encoder module, a speech codec decoder module and post-processing modules. The pre-processing and post-processing modules are implemented on a DSP/VLIW processor, while the speech encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the talk time.
    Type: Application
    Filed: June 3, 2020
    Publication date: March 18, 2021
    Inventor: Narasimhan Vijay Anand
  • Patent number: 10390309
    Abstract: The present invention provides a system and method for optimizing power consumption in mobile devices. The system comprises a speech codec encoder module and a speech codec decoder module. The number of CPU/DSP/VLIW processor cycles taken to encode and decode the speech signals are significantly reduced to draw lower current by the mobile device. The significant reduction of processor cycles in the speech codec modules enables reduction of power consumption in the talk time. Thus, the invention provides a simple method of optimizing power consumption by reducing number of processor cycles to compress/decompress speech signal of the speech codec modules in mobile devices.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 20, 2019
    Inventor: Narasimhan Vijay Anand