Abstract: The invention relates to a system and method for prioritising one or more data processing operations in a computer storage system, the computer storage system including a plurality of modules, the method comprising receiving a command indicating one or more data processing operations to which priority is to be assigned and interfacing with each of the modules so as to prioritise the one or more data processing operations over other data processing operations.

Abstract: A method, a system and a computer program for determining device criticality during SAN reconfiguration operations comprising the steps of building the SAN connectivity graph and mapping the reconfiguration on SAN connectivity graph; locating the affected host systems; and determining the device criticality for each of the affected host systems. The hosts systems may also be provided with impact analysis agents to generate device criticality on host systems and a central agent to aggregate the device criticality from impact analysis agent and provide feedback to data center administrator.

Abstract: The method, apparatus and system of an I/O forwarding technique for multi-interrupt capable I/O devices are disclosed. In one embodiment, a method of transferring an I/O request in a cache-coherent non-uniform memory access (ccNUMA) computer system including multiple cells (e.g., each cell may include multiple processors) that are connected via a system interconnect, includes receiving an I/O request from one of the multiple processors associated with one of the multiple cells in the ccNUMA computer system, associating a processor, corresponding to a multi-interrupt capable I/O interface that is servicing the I/O request, located in the one of the multiple cells as a lead processor, and executing an I/O initiation path and a completion path associated with the received I/O request on the lead processor upon associating the lead processor corresponding to the multi-interrupt capable I/O interface.

Abstract: A method and system for processing an input/output request on a multiprocessor computer system comprises pinning a process down to a processor issuing the input/output request. An identity of the processor is passed to a device driver which selects a device adapter request queue whose interrupt is bound to the identified processor and issues the request on that queue. The device accepts the request from the device adapter, processes the request and raises a completion interrupt to the identified processor. On completion of the input/output request the process is un-pinned from the processor. In an embodiment the device driver associates a vector of the identified processor with the request and the device, on completion of the request, interrupts the processor indicated by the vector.