Patents by Inventor Narayanan Balasubramanian
Narayanan Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7397090Abstract: A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.Type: GrantFiled: June 9, 2005Date of Patent: July 8, 2008Assignee: Agency for Science, Technology and ResearchInventors: Shajan Mathew, Lakshmi Kanta Bera, Narayanan Balasubramanian
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Publication number: 20080064153Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.Type: ApplicationFiled: October 30, 2007Publication date: March 13, 2008Inventors: Patrick Qiang Lo, Wei Loh, Ranganathan Nagarajan, Narayanan Balasubramanian
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Patent number: 7294890Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.Type: GrantFiled: March 3, 2005Date of Patent: November 13, 2007Assignee: Agency for Science, Technology and ResearchInventors: Patrick Guo Qiang Lo, Wei Yip Loh, Ranganathan Nagarajan, Narayanan Balasubramanian
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Publication number: 20060226483Abstract: A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Inventors: Patrick Lo, Lakshmi Bera, Wei Loh, Balakumar Subramanian, Narayanan Balasubramanian
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Publication number: 20060199321Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.Type: ApplicationFiled: March 3, 2005Publication date: September 7, 2006Inventors: Patrick Guo Lo, Wei Loh, Ranganathan Nagarajan, Narayanan Balasubramanian
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Publication number: 20050275035Abstract: A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.Type: ApplicationFiled: June 9, 2005Publication date: December 15, 2005Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Shajan Mathew, Lakshmi Bera, Narayanan Balasubramanian
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Publication number: 20050130361Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.Type: ApplicationFiled: January 14, 2005Publication date: June 16, 2005Inventors: Narayanan Balasubramanian, Richard Hammond
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Publication number: 20050056827Abstract: Three configurations of double barrier resonant tunneling diodes (RTD) are provided along with methods of their fabrication. The tunneling barrier layers of the diode are formed of low band offset dielectric materials and produce a diode with good I-V characteristics including negative differential resistance (NDR) with good peak-to-valley ratios (PVR). Fabrication methods of the RTD start with silicon-on-insulator substrates (SOI), producing silicon quantum wells, and are, therefore, compatible with main stream CMOS technologies such as those applied to SOI double gate transistor fabrication. Alternatively, Ge-on-insulator or SiGe-on-insulator substrates can be used if the quantum well is to be formed of Ge or SiGe. The fabrication methods include the formation of both vertical and horizontal silicon quantum well layers. The vertically formed layer may be oriented so that its vertical sides are in any preferred crystallographic plane, such as the 100 or 110 planes.Type: ApplicationFiled: January 29, 2004Publication date: March 17, 2005Inventors: Ming Li, Jagar Singh, Yong Hou, Narayanan Balasubramanian, Fujiang Lin
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Patent number: 6846720Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.Type: GrantFiled: June 18, 2003Date of Patent: January 25, 2005Assignee: Agency for Science, Technology and ResearchInventors: Narayanan Balasubramanian, Richard Hammond
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Publication number: 20040259314Abstract: A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.Type: ApplicationFiled: June 18, 2003Publication date: December 23, 2004Applicant: Institute Of Microelectronics & Amberwave Systems CorporationInventors: Narayanan Balasubramanian, Richard Hammond
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Publication number: 20040245578Abstract: A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AINx) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.Type: ApplicationFiled: April 16, 2004Publication date: December 9, 2004Inventors: Chang Seo Park, Byung Jin Cho, Narayanan Balasubramanian
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Patent number: 6664596Abstract: A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.Type: GrantFiled: October 16, 2002Date of Patent: December 16, 2003Assignee: Institute of MicroelectronicsInventors: Jun Cai, Pang Dow Foo, Narayanan Balasubramanian
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Publication number: 20030085448Abstract: A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.Type: ApplicationFiled: October 16, 2002Publication date: May 8, 2003Applicant: INSTITUTE OF MICROELECTRONICSInventors: Jun Cai, Pang Dow Foo, Narayanan Balasubramanian
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Patent number: 6551937Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.Type: GrantFiled: August 23, 2001Date of Patent: April 22, 2003Assignees: Institute of Microelectronics, National University of SingaporeInventors: Cai Jun, Ren Chang Hong, Ranganathan Nagarajan, Narayanan Balasubramanian, Yung Chii Liang
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Publication number: 20030040185Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep tenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches.Type: ApplicationFiled: August 23, 2001Publication date: February 27, 2003Applicant: Institute of MicroelectronicsInventors: Cai Jun, Ren Chang Hong, Ranganathan Nagarajan, Narayanan Balasubramanian, Yung Chii Liang
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Patent number: 6489203Abstract: A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.Type: GrantFiled: May 7, 2001Date of Patent: December 3, 2002Assignee: Institute of MicroelectronicsInventors: Jun Cai, Pang Dow Foo, Narayanan Balasubramanian
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Publication number: 20020164844Abstract: A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.Type: ApplicationFiled: May 7, 2001Publication date: November 7, 2002Applicant: Institute of MicroelectronicsInventors: Jun Cai, Pang Dow Foo, Narayanan Balasubramanian
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Patent number: 6468853Abstract: A structure and a process for manufacturing semiconductor devices with improved oxide coverage on the corners of a shallow trench isolation structure is described. The STI trench is etched using a pad oxide and silicon nitride layers as patterning elements. After trench etch, a thin conformal layer of either amorphous, epitaxial or polysilicon is deposited over the silicon nitride and within the trench and annealed. Where the silicon has been deposited on the silicon bottom and sides of the open trench, the annealing effectively forms a single crystal or epitaxial silicon. Next a silicon oxide liner is grown over the conformal silicon layer. The trench is then filled with silicon oxide, the structure is planarized by either chemical mechanical polishing or etching, and the nitride and pad oxide is removed This leaves a polysilicon film on the vertical edges of the filler oxide which extends slightly above the surface of the silicon substrate.Type: GrantFiled: August 18, 2000Date of Patent: October 22, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Palanivel Balasubramanian, Yelehanka Ramachandramurthy Pradeep, Chivkula Subrahmanyam, Narayanan Balasubramanian
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Patent number: 6235591Abstract: A method of fabricating gate oxides of different thicknesses has been achieved. Active area isolations are provided in a silicon substrate to define low voltage sections and high voltage sections in the silicon substrate. A sacrificial oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the sacrificial oxide layer. A masking oxide layer is deposited overlying the silicon nitride layer. The masking oxide layer is patterned to form a hard mask overlying the low voltage sections. The silicon nitride layer is etched through where exposed by the hard mask thereby exposing the sacrificial oxide layer overlying the high voltage section. The exposed sacrificial oxide layer and the hard mask are etched away. A thick gate oxide layer is grown overlying the silicon substrate in the high voltage section. The silicon nitride layer is etched away. The sacrificial oxide layer overlying the low voltage section is etched away.Type: GrantFiled: October 25, 1999Date of Patent: May 22, 2001Assignee: Chartered Semiconductor Manufacturing CompanyInventors: Narayanan Balasubramanian, Yelehanka Ramachandamurthy Pradeep, Jia Zhen Zheng, Alan Cuthbertson
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Patent number: 6200887Abstract: A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate.Type: GrantFiled: January 24, 2000Date of Patent: March 13, 2001Assignee: Chartered Semiconductor Manufacturing LtdInventors: Palanivel Balasubramaniam, Narayanan Balasubramanian, Yelehanka Ramachandramurthy Pradeep, Arjun Kantimahanti