Patents by Inventor Narayanan Ramani

Narayanan Ramani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9984376
    Abstract: The present disclosure relates to method and system for automatically identifying one or more issues in one or more tickets of an organization. An issue identification system retrieves a sequence pattern from ticket data received from one or more data sources. The issue identification system generates one or more first sub-sequence patterns of the n-grams from the sequence pattern. Further, frequency of occurrence and Part-of-Speech (POS) weightage of each of the one or more first sub-sequence patterns of the n-grams are determined by the issue identification system. A first score is determined for each of the one or more first sub-sequence patterns of the n-grams based on both the frequency and the POS weightage. Upon determining the first score, the issue identification system identifies one or more issues in the one or more tickets automatically based on the first sub-sequence pattern of the n-grams associated with a highest first score.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 29, 2018
    Assignee: WIPRO LIMITED
    Inventors: Venkatakrishnan Rajaram, Narayanan Ramani Konnayar, Ria Chakraborty, Malathi Bellam Soundararajan
  • Publication number: 20170262858
    Abstract: The present disclosure relates to method and system for automatically identifying one or more issues in one or more tickets of an organization. An issue identification system retrieves a sequence pattern from ticket data received from one or more data sources. The issue identification system generates one or more first sub-sequence patterns of the n-grams from the sequence pattern. Further, frequency of occurrence and Part-of-Speech (POS) weightage of each of the one or more first sub-sequence patterns of the n-grams are determined by the issue identification system. A first score is determined for each of the one or more first sub-sequence patterns of the n-grams based on both the frequency and the POS weightage. Upon determining the first score, the issue identification system identifies one or more issues in the one or more tickets automatically based on the first sub-sequence pattern of the n-grams associated with a highest first score.
    Type: Application
    Filed: March 31, 2016
    Publication date: September 14, 2017
    Inventors: Venkatakrishnan Rajaram, Narayanan Ramani Konnayar, Ria Chakraborty, Malathi Bellam Soundararajan
  • Publication number: 20070235813
    Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.
    Type: Application
    Filed: April 10, 2006
    Publication date: October 11, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Da Zhang, Venkat Kolagunta, Narayanan Ramani, Bich-Yen Nguyen
  • Publication number: 20070190711
    Abstract: A method of forming a semiconductor device, the method includes forming a gate dielectric over the semiconductor substrate, exposing the gate dielectric to a halogen, and incorporating the halogen into the gate dielectric. In one embodiment, the halogen is fluorine. In one embodiment, the gate dielectric is also exposed to nitrogen and the nitrogen is incorporated into the gate dielectric. In one embodiment, the gate dielectric is a metal oxide.
    Type: Application
    Filed: February 10, 2006
    Publication date: August 16, 2007
    Inventors: Tien Luo, Olubunmi Adetutu, Eric Luckowski, Narayanan Ramani
  • Publication number: 20070069311
    Abstract: A transistor structure of an electronic device can include a gate dielectric layer and a gate electrode. The gate electrode can have a surface portion between the gate dielectric layer and the rest of the gate electrode. The surface portion can be formed such that another portion of the gate electrode primarily sets the effective work function in the finished transistor structure.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 29, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Olubunmi Adetutu, Tien Luo, Narayanan Ramani