Abstract: Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Abstract: Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

Abstract: An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.

Abstract: A method and an apparatus to track transition of a flag signal for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes one or more memory devices, coupled to a data bus, to receive a command signal, wherein the command signal initiates a set of data transfer operations to transfer data between the data bus and one of the one or more memory devices; and a timing unit, coupled to the one or more memory devices, to receive the command signal, a flag signal, and a memory select signal, the timing unit to generate a trigger signal, in response to a transition of the flag signal, to complete the data transfer operations if the memory select signal corresponds to the one of the one or more memory devices. Other embodiments have been claimed and described.

Abstract: A method of addressing a memory device on a memory module includes determining whether a command has been issued to the memory module. An evaluation state is entered if the command has been issued. While in the evaluation state, it is determined whether an identification signal has been issued for the memory device to initiate action. Action is initiated if the identification signal indicates that the memory device is to respond to the command issued.

Abstract: A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.

Abstract: A method of addressing a memory device on a memory module includes determining whether a command has been issued to the memory module. An evaluation state is entered if the command has been issued. While in the evaluation state, it is determined whether an identification signal has been issued for the memory device to initiate action. Action is initiated if the identification signal indicates that the memory device is to respond to the command issued.

Abstract: Memory modules, memory systems, and computing devices are described which include memory buffer devices that buffer signals of memory devices. In some embodiments, the memory buffer devices are positioned to reduce the circuit board footprint of the memory buffer devices.

Abstract: A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.

Abstract: A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable the data trigger scheme to work in a more heavily loaded configuration where there is more timing skew.

Abstract: A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable this data trigger scheme to work even in heavily loaded configurations where there is more timing skew.

Abstract: A computer system that includes at least two host agents is provided. The computer system further includes a chipset that includes a resource to be shared by the at least two host agents. The chipset is coupled to the at least two host agents. The chipset prevents a first host agent, that occupies the shared resource to access the shared resource until a second host agent, has made progress in accessing said shared resource.

Abstract: Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

Abstract: A computer system that includes at least two host agents is provided. The computer system further includes a chipset that includes a resource to be shared by the at least two host agents. The chipset is coupled to the-at least two host agents. The chipset prevents a first host agent, that occupies the shared resource to access the shared resource until a second host agent, has made progress in accessing said shared resource.

Abstract: A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the first read request, the host bridge asserts a following second read request to the SM.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.

Abstract: A method and an apparatus for a synchronous DRAM-type memory control is provided that allows continued and accurate data transfer to and from a synchronous DRAM (syncDRAM) memory for special cases where data is not ready to be transferred. In the event that data is not ready to be transferred between a destination device and the syncDRAM, transfer of data is suspended. Concurrently, at the address from which data was not ready to be transferred, the address is latched by a syncDRAM interface that communicates with the system memory control and the syncDRAM memory. In the event of a read cycle, back-to-back read requests are performed until data can be transferred. In the event of a write request, a mask command is asserted to mask out the data address in the syncDRAM until data is ready to be written to the address, wherein the write request is then reasserted. For both read and write cycles, when data is subsequently ready to be transferred, data transfer is resumed at the latched address.

Abstract: A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to read and flushes the data to the storage element prior to the component reading the address associated with the data in the storage element.

Abstract: A synchronous DRAM-type memory control is provided that allows continued and accurate data transfer to and from a synchronous DRAM (syncDRAM) memory for special cases where data is not ready to be transferred. In the event that data is not ready to be transferred between a destination device and the syncDRAM, transfer of data is suspended. Concurrently, at the address from which data was not ready to be transferred, the address is latched by a syncDRAM interface that communicates with the system memory control and the syncDRAM memory. In the event of a read cycle, back to back read requests are asserted until data can be transferred. In the event of a write request, a mask command is asserted to mask out the data address in the syncDRAM until data is ready to be written to the address, wherein the write request is then reasserted. For both read and write cycles, when data is subsequently ready to be transferred, data transfer is resumed at the latched address.

Abstract: A syncDRAM memory interface is provided that is capable of extending data burst during a data transfer in a syncDRAM memory so as to provide a continuous draw of data from the syncDRAM memory banks. Included in the interface is a pipeline request path configured to receive pipeline request data from a microprocessor, a pipeline command generator configured to generate pipeline commands and transfer them to the syncDRAM memory such that a pipeline data transfer command is transferred to the syncDRAM memory in parallel with a primary command generated from the microprocessor and sent to the syncDRAM. This pipeline data transfer command is received by the syncDRAM through the same internal address latch used in response to a primary data transfer request. A pipeline arm generator is also provided to communicate with the pipeline request path and the data transfer controller to indicate that the syncDRAM interface is ready to transfer data in response to a pipeline request.