Abstract: A lighting network for altering a power factor of an alternating current, AC, supply (5). The lighting network comprises luminaires (2, 3) having reactive components of a first reactive type which are controllably coupled, by a controller, to the AC supply so as to adjust the power factor of the AC supply. The controller controls the coupling of the luminaires based on a power factor signal indicative of a power factor of the AC supply, which is influenced by an appliance (6) with a reactive load of a second reactive type, which appliance is different to any one of the luminaires. Preferably, the first reactive type is capacitive, and the second reactive type is inductive.

Abstract: The invention relates playing back video with subtitles. A playback apparatus (20) is provided for playback of video data (e.g. in DivX-format) and corresponding subtitle data files from a record carrier. The one or more subtitle data files may be stored on the carrier without language metadata of the subtitles. The apparatus comprises units operable to access the one or more subtitle data files on the associated record carrier, fetch a content sample (21-26) of the subtitle data files, and output to a display unit (3) a signal representing the fetched content samples. The user may then select one of the content samples and thus identify the desired subtitle file to be reproduced.

Abstract: A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register.

Abstract: A data processing system in a multi-tasking environment is provided. The data processing system comprises at least one processing unit (1) for an interleaved processing of the multiple tasks. Each of the multiple tasks comprises available data associated to it and a corresponding waiting time. In addition, a task scheduler (2) is provided for scheduling the multiple tasks to be processed by the at least one processing unit (1). The task scheduling is performed based on the amount of data available for the one of the multiple tasks and based on the waiting time of the data to get processed by that task.

Abstract: A data processing system is provided. The data processing system comprises at least one processor (P) for processing data according to a set of instructions. The processors are coupled by a bus means (BM). Furthermore, a debugging means (DM) is provided to detect the occurrence of events and the corresponding point of time of the occurrence on the bus means (BM). If predefined events occur at, within and/or after/before predefined points in time, the debugging mode is switched on.

Abstract: A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register.

Abstract: The apparatus of the present invention improves performance of computing systems by enabling a multi-core or multi-processor system to deterministically identify cache memory (100) blocks that are ripe for victimization and also prevent victimization of memory blocks that will be needed in the immediate future. To achieve these goals, the system has a FIFO with schedule information available in the form of Estimated Production Time (EPT) (102) and Estimated Consumption Time (ECT) (104) counters to make suitable pre-fetch and write-back decisions so that data transmission is overlapped with processor execution.