Patents by Inventor Naresh R. Shanbhag

Naresh R. Shanbhag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for improving power conversion for advanced electronic circuits
    Patent number: 9116692
    Abstract: A system includes a circuit having a plurality of electronic function blocks interconnected in series, a power source unit coupled to the circuit, for supplying power to the plurality of electronic function blocks, and a control unit coupled to each of the plurality of the electronic function blocks and to the power source unit. The control unit is configured to monitor activity levels of each of the electronic function blocks, and adjusts the activity level of each of the plurality of electronic function blocks. The control unit determines a voltage level suitable for the corresponding adjusted activity level, and adjusts the power supplied to each of the plurality of electronic function blocks in order to achieve the corresponding determined voltage level at each of the plurality of electronic function blocks.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 25, 2015
    Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Philip T. Krein, Roy H. Campbell, Naresh R. Shanbhag
  • Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator
    Patent number: 8102938
    Abstract: A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: January 24, 2012
    Assignee: Finisar Corporation
    Inventors: Jonathan B. Ashbrook, Andrew C. Singer, Naresh R. Shanbhag, Robert J. Drost
  • TUNING SYSTEM AND METHOD USING A SIMULATED BIT ERROR RATE FOR USE IN AN ELECTRONIC DISPERSION COMPENSATOR
    Publication number: 20090262870
    Abstract: A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 22, 2009
    Applicant: FINISAR CORPORATION
    Inventors: Jonathan B. Ashbrook, Andrew C. Singer, Naresh R. Shanbhag, Robert J. Drost