Abstract: A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation.

Abstract: In an adder for floating point data, two floating point data are adjusted so that the exponent parts have the same value and the resulting adjusted mantissa parts are added. A first shift signal is generated on the basis of the result of the added mantissa parts and having a value necessary for normalization of the addition result, and a second shift signal is generated having a value equal to the difference between the adjusted exponent part of the floating point data and a minimum value predetermined for an exponent of any floating point data at which underflow occurs. The result of addition of the adjusted mantissa parts is shifted on the basis of said second shift signal or said first shift signal depending on whether or not an underflow occurs.

Abstract: According to the present invention, a normalized floating point type multiplier circuit including a multiplier for mantissa's multiplication and an adder for exponent's addition is equipped with both a detector circuit for detecting over- and under-flows and a compensation circuit for compensating the output of said multiplier without any programming, when the over- and under-flows are detected, so that the multiplying speed can be improved.

Abstract: In a gain control circuit, an electric power calculating circuit is connected to a variable gain amplifier and a gain setting circuit for generating a gain control signal applied to the variable gain amplifier to control the gain thereof.

Abstract: A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.

Abstract: An equalizer apparatus suitable for use in a MODEM for receiving a signal having passed through a number of carrier-band lines is disclosed in which the number of carrier-band lines is detected from a training signal, and electrical connection of a fixed equalizer to a variable equalizer is controlled on the basis of the number of carrier-band lines, in order to form a precise, simple automatic equalizer apparatus.

Abstract: A signal processing system detects the transmission characteristics of a channel thereby to compensate the output waveform of the channel into the most-optimum state. The impulse response of the channel is detected by transmitting a code having a keen autocorrelation from the transmission end and by determining the correlation between the received signal of the code transmitted and the same code of the aforementioned code at a reception end.

Abstract: A recursive-type digital filter comprising a calculation circuit. The calculation circuit is arranged to multiply an input signal including at least m-bit signal x.sub.n inputted at a predetermined sampling period and an output signal y.sub.n-k fed back to the input of the calculation circuit in accordance with the input signal x.sub.n after being subjected to a delay of k sampling periods by a.sub.k and b.sub.k coefficients corresponding to the filter characteristics, respectively, and then the products are added thereby to produce data y.sub.n of (m+l) bits satisfying, ##EQU1## and serially deliver the upper m-bit data of the data y.sub.n as an output signal corresponding to the input signal x.sub.n.The filter further comprises a delay circuit for feeding back to the input of the calculation circuit a part of the round off data including the upper (m+1)th bit of the data y.sub.n so that the b.sub.k coefficient is multiplied by the fedback data of the upper (m+1)th bit and the product is added to the data y.

Abstract: A circuit for varying the gain of an amplifier circuit linearly in decibel by the use of a digital code signal varying linearly, wherein a resistance network to be connected between an amplifier having a fixed gain and an input or output portion for the amplification is connected and the gain of the amplifier as well as the values of resistance elements constituting the resistance network is set so that the transfer function of the amplifier circuit may become: ##EQU1## .

Abstract: An inductorless variable equalizer comprises input and output terminals. A first transmission network is situated in the forward path between the input and output terminals and has a variable transfer coefficient; second and third transmission networks are situated in the feedback and feedforward paths, respectively, between the input and output terminals. Each of these networks has a fixed transfer coefficient and the transfer coefficients of the feedback and feedforward networks having polarities opposite each other.