Abstract: A disclosed system may include (1) a memory package having a physical memory and optical circuitry, (2) a processor package, separate and distinct from the memory package, having at least one physical processor and additional optical circuitry, and (3) an optical medium communicatively coupling the optical circuitry of the memory package with the additional optical circuitry of the processor package. Various other systems, apparatuses, and methods are also disclosed.

Abstract: The disclosed computer-implemented method may include receiving, from a host via a cache-coherent interconnect, a request to access an address of a coherent memory space of the host. When the request is to write data, the computer-implemented method may include (1) performing, after receiving the data, a post-processing operation on the data to generate post-processed data and (2) writing the post-processed data to a physical address of a device-attached physical memory mapped to the address. When the request is to read data, the computer-implemented method may include (1) reading the data from the physical address of a device-attached physical memory mapped to the address, (2) performing, before responding to the request, a pre-processing operation on the data to generate pre-processed data, and (3) returning the pre-processed data to the external host via the cache-coherent interconnect. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A disclosed system may include a disaggregated artificial intelligence (AI) operation accelerator including a dense AI operation accelerator configured to accelerate dense AI operations and a sparse AI operation accelerator, physically separate from the dense AI operation accelerator, configured to accelerate sparse AI operations. The system may also include a scheduler that includes (1) a receiving module that receives an AI operation, (2) an identifying module that identifies the AI operation as a dense AI operation or sparse AI operation, and (3) a directing module that directs (a) the dense AI operation accelerator to accelerate identified dense AI operations, and (b) the sparse AI operation accelerator to accelerate identified sparse AI operations. The system may also include a physical processor that executes the receiving module, the identifying module, and the directing module. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed IC package may include (1) an IC die carrying electronic circuitry, (2) an encapsulation material that at least partially covers the IC die, where the encapsulation material defines a plurality of cavities in a top surface of the encapsulation material, (3) a plurality of microfans located in the plurality of cavities, and (4) a plurality of sensors embedded in the encapsulation material, where each sensor of the plurality of sensors produces a signal indicating a temperature at a location of the sensor. Various other IC packages, as well as associated cooling systems and methods, are also disclosed.

Abstract: A disclosed system may include (1) a memory package having a physical memory and optical circuitry, (2) a processor package, separate and distinct from the memory package, having at least one physical processor and additional optical circuitry, and (3) an optical medium communicatively coupling the optical circuitry of the memory package with the additional optical circuitry of the processor package. Various other systems, apparatuses, and methods are also disclosed.

Abstract: The disclosed computer-implemented method may include (1) receiving, by a first internal physical processor of an accelerator from an external processor, a request to access a result of executing a sensitive application within a secure execution zone of the accelerator having (a) a second internal physical processor and (b) physical memory accessible to the second internal physical processor but inaccessible to the first internal physical processor and the external processor, (2) executing, by the second internal physical processor within the secure execution zone, the sensitive application from the physical memory to generate the result, (3) making, by the second internal physical processor, the result accessible outside of the secure execution zone, and (4) relaying, by the first internal physical processor, the result to the external processor. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method may include receiving, from a host via a cache-coherent interconnect, a request to access an address of a coherent memory space of the host. When the request is to write data, the computer-implemented method may include (1) performing, after receiving the data, a post-processing operation on the data to generate post-processed data and (2) writing the post-processed data to a physical address of a device-attached physical memory mapped to the address. When the request is to read data, the computer-implemented method may include (1) reading the data from the physical address of a device-attached physical memory mapped to the address, (2) performing, before responding to the request, a pre-processing operation on the data to generate pre-processed data, and (3) returning the pre-processed data to the external host via the cache-coherent interconnect. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method may include (1) receiving, from an external host processor via a cache-coherent interconnect, a request to access a host address of a coherent memory space of the external host processor, (2) when the request is to read data from the host address, (a) performing an in-line transformation on the data to generate second data and (b) writing the second data to the physical address of the device-attached physical memory mapped to the host address, and (3) when the request is to read data from the host address, (a) reading the data from the physical address of the device-attached physical memory mapped to the host address, (b) performing a reversing in-line transformation on the data to generate second data, and (c) returning the second data to the external host processor via the cache-coherent interconnect. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A first set of 64 bytes of data and a second set of 64 bytes of data are received. A first set of eight error-correcting code (ECC) bytes for the first set of 64 bytes of data and a second set of eight ECC bytes for the second set of 64 bytes of data are calculated. The first set of 64 bytes of data, the second set of 64 bytes of data, the first set of eight ECC bytes, and the second set of eight ECC bytes are sent to one or more 5th generation double data rate (DDR5) synchronous dynamic random-access memory (SDRAM) modules through a DDR5 dual-channel in a single burst, wherein the DDR5 dual-channel comprises a first data channel and a second data channel, and wherein the first data channel and the second data channel are driven by a same clock signal.

Abstract: The disclosed IC package may include (1) an IC die carrying electronic circuitry, (2) an encapsulation material at least partially covering the IC die, where (a) the encapsulation material defines a plurality of microchannels within the encapsulation material and (b) the plurality of microchannels are configured to carry fluid through the encapsulation material between one or more microchannel inlets and one or more microchannel outlets located at an exterior of the encapsulation material, (3) a plurality of flow valves positioned in the plurality of microchannels, and (4) a plurality of sensors, where each sensor of the plurality of sensors produces a signal indicating a temperature at a location of the sensor. Various other IC packages, as well as associated cooling systems and methods, are also disclosed.

Abstract: The disclosed IC package may include (1) an IC die carrying electronic circuitry, (2) an encapsulation material that at least partially covers the IC die, where the encapsulation material defines a plurality of cavities in a top surface of the encapsulation material, (3) a plurality of microfans located in the plurality of cavities, and (4) a plurality of sensors embedded in the encapsulation material, where each sensor of the plurality of sensors produces a signal indicating a temperature at a location of the sensor. Various other IC packages, as well as associated cooling systems and methods, are also disclosed.

Abstract: A controller device is disclosed. The controller device comprises a communication interface that is configured to receive a data operation request via an interconnect bus. The controller device comprises an integrated interconnect protocol component that is configured to handle communication via the interconnect bus that supports coherency across a plurality of different processing devices external to the controller device. An integrated memory or storage controller component on the same controller device is configured to handle the data operation request including by being configured to manage communication with a memory or data storage device external to the controller device.

Abstract: An expansion card may include a printed circuit board and a hardware accelerator that is disposed on the printed circuit board. The hardware accelerator may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may also offload a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task. The expansion card may further include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into an expansion socket of the computing device. The edge connector may couple the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket. The edge socket may also include a pinout that is more compact than a pinout specification defined for the computing bus. Various other apparatuses, systems, and methods are also disclosed.

Abstract: An indication to share a content item associated with a residential cache appliance and a first social networking account is received. A network address of the residential cache appliance is associated with the content item. A cache map of available residential cache appliances is maintained to implement a distributed cache store. For one or more of the available residential cache appliances, the cache map identifies at least an associated social networking account, an associated network address, associated cache appliance stored content items, and an associated setting. From a requester device associated with a second social networking account, a request for the content item is received. In response to the request, based at least in part on the cache map, the requester device is directed to the residential cache appliance to obtain at least a portion of the content item.

Abstract: An expansion card may include a printed circuit board and a hardware accelerator that is disposed on the printed circuit board. The hardware accelerator may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may also offload a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task. The expansion card may further include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into an expansion socket of the computing device. The edge connector may couple the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket. The edge socket may also include a pinout that is more compact than a pinout specification defined for the computing bus. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method for performing client-side content inference may include (1) receiving a request to upload, from a client-side device to a server-side device, a content item that includes a first sequence of bytes and a second sequence of bytes, (2) identifying a model configured to output a classification for sequences of bytes, (3) using, at the client-side device, the model to derive a first classification for the first sequence, (4) using, at the client-side device, the model to derive a second classification for the second sequence, and (5) uploading, in response to the request, the content item to the server-side device by (a) uploading the first sequence, (b) uploading the first classification substantially contemporaneous with uploading the first sequence, (c) uploading the second sequence, and (d) uploading the second classification substantially contemporaneous with uploading the second sequence. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An expansion card may include a printed circuit board and a hardware accelerator that is disposed on the printed circuit board. The hardware accelerator may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may also offload a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task. The expansion card may further include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into an expansion socket of the computing device. The edge connector may couple the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket. The edge socket may also include a pinout that is more compact than a pinout specification defined for the computing bus. Various other apparatuses, systems, and methods are also disclosed.

Abstract: An indication to share a content item associated with a residential cache appliance and a first social networking account is received. A network address of the residential cache appliance is associated with the content item. A cache map of available residential cache appliances is maintained to implement a distributed cache store. For one or more of the available residential cache appliances, the cache map identifies at least an associated social networking account, an associated network address, associated cache appliance stored content items, and an associated setting. From a requester device associated with a second social networking account, a request for the content item is received. In response to the request, based at least in part on the cache map, the requester device is directed to the residential cache appliance to obtain at least a portion of the content item.