Patents by Inventor Naruhiko Aramaki

Naruhiko Aramaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10956238
    Abstract: A programmable controller includes a plurality of processor cores, an input unit, an allocating unit, a transmitting unit, a power controlling unit, an updating unit, and an executing unit. The allocating unit allocates any one of the plurality of processing to each of the plurality of processor cores. The transmitting unit transmits an allocation result of the processing to a management device. The power controlling unit restarts when the allocation of the processing is changed in the management device and the input unit inputs the changed setup data. The updating unit updates the allocation to the plurality of processor cores based on the setup data after the restart. The executing unit executes the plurality of processing based on the allocation, and when the allocation is changed, executes the plurality of processing based on the changed allocation.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Naruhiko Aramaki, Hiroyuki Fujieda
  • Publication number: 20200151033
    Abstract: A programmable controller includes a plurality of processor cores, an input unit, an allocating unit, a transmitting unit, a power controlling unit, an updating unit, and an executing unit. The allocating unit allocates any one of the plurality of processing to each of the plurality of processor cores. The transmitting unit transmits an allocation result of the processing to a management device. The power controlling unit restarts when the allocation of the processing is changed in the management device and the input unit inputs the changed setup data. The updating unit updates the allocation to the plurality of processor cores based on the setup data after the restart. The executing unit executes the plurality of processing based on the allocation, and when the allocation is changed, executes the plurality of processing based on the changed allocation.
    Type: Application
    Filed: December 4, 2017
    Publication date: May 14, 2020
    Applicant: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Naruhiko ARAMAKI, Hiroyuki FUJIEDA
  • Patent number: 8281203
    Abstract: When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Murakami, Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoichi Takayanagi, Motohiko Okabe
  • Patent number: 8131900
    Abstract: A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: March 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoshito Sameda, Hiroshi Nakatani, Motohiko Okabe, Yukitaka Yoshida
  • Publication number: 20120030402
    Abstract: A PCI Express TLP processing circuit (10) comprises: a plurality of reception processing sections (2a1); a transmission processing section (2b); and a multiplexer (2c1) that performs transmission to the transmission processing section, selecting one of the reception processing sections; and at least a reception processing section comprises: a redundancy code generating circuit (12); an LCRC/sequential number detection circuit (13); a buffer memory (14); a packet control circuit section (16) that controls transmission for normal transmission to the transmission destination of the TLP in question or for nullifying transmission; and the transmission processing section comprises: a sequential number generating circuit (19); an LCRC generating circuit (20) and a relay circuit error detection circuit (21), whereby data integrity of the transmitted TLP can be guaranteed.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 2, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki MURAKAMI, Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoichi Takayanagi, Motohiko Okabe
  • Publication number: 20100251055
    Abstract: When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.
    Type: Application
    Filed: March 31, 2010
    Publication date: September 30, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Murakami, Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoichi Takayanagi, Motohiko Okabe
  • Publication number: 20090287867
    Abstract: A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 19, 2009
    Inventors: Jun Takehara, Naruhiko Aramaki, Toshikazu Kawamura, Yoshito Sameda, Hiroshi Nakatani, Motohiko Okabe, Yukitaka Yoshida