Patents by Inventor Naruhiko Kaji
Naruhiko Kaji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7371654Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: GrantFiled: April 3, 2006Date of Patent: May 13, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Publication number: 20060189092Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: ApplicationFiled: April 3, 2006Publication date: August 24, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Patent number: 7084077Abstract: A method for fabricating a high density semiconductor integrated circuit device with a multilayer interconnect wiring structure is disclosed. This structure has a low-dielectric constant insulator film including an organic thin-film with its dielectric constant ranging from about 2.0 to about 2.4. To fabricate the multilayer wiring structure, a substrate with an inorganic film for use as an underlayer dielectric film is prepared. Then, apply plasma processing, such as plasma-assisted chemical vapor-phase growth, to a top surface of the inorganic underlayer dielectric film in environment that contains therein organic silane-based chemical compounds, thereby to form on the inorganic film surface a hydrophobic surface layer with a contact angle with water being 50° or higher. Next, form on the plasma-processed hydrophobic surface an organic film including a fluorinated aromatic carbon hydride polymer film.Type: GrantFiled: August 27, 2004Date of Patent: August 1, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Naruhiko Kaji, Katsumi Yoneda
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Patent number: 6938638Abstract: A gas-circulating processing apparatus which comprises a processing chamber, a gas feeding piping, a gas supply piping, a first exhaust mechanism discharging a gas from the processing chamber, a second exhaust mechanism discharging a portion of a gas discharged from the first exhaust mechanism, a back pressure adjusting mechanism interposed between the first exhaust mechanism and the second exhaust mechanism to adjust a back pressure of the first exhaust mechanism, and a gas circulating piping which is configured to combine another portion of the gas that has been discharged from the first exhaust mechanism with a processing gas supplied from the gas supply piping, wherein the gas feeding piping has a larger inner diameter than that of the gas supply, or the processing gas is introduced into the first exhaust mechanism, or a first heater is provided to heat at least part of the circulating route.Type: GrantFiled: December 27, 2001Date of Patent: September 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Kubota, Rempei Nakata, Naruhiko Kaji, Itsuko Sakai, Takashi Yoda
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Publication number: 20050181576Abstract: A method of forming an inorganic porous film comprises applying, to a support, an inorganic material composition including a mixture of a silicon oxide precursor containing at least one hydrolyzable silane compound and a pore-generating material, thereby forming a film, drying the film, contacting the film after the drying with a supercritical fluid to remove the pore-generating material; and baking the film after the removal of the pore-generating material.Type: ApplicationFiled: May 29, 2003Publication date: August 18, 2005Applicant: Semiconductor Leading edge Technologies, IncInventors: Shinichi Ogawa, Takashi Nasuno, Naruhiko Kaji
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Publication number: 20050085097Abstract: A method for fabricating a high density semiconductor integrated circuit device with a multilayer interconnect wiring structure is disclosed. This structure has a low-dielectric constant insulator film including an organic thin-film with its dielectric constant ranging from about 2.0 to about 2.4. To fabricate the multilayer wiring structure, a substrate with an inorganic film for use as an underlayer dielectric film is prepared. Then, apply plasma processing, such as plasma-assisted chemical vapor-phase growth, to a top surface of the inorganic underlayer dielectric film in environment that contains therein organic silane-based chemical compounds, thereby to form on the inorganic film surface a hydrophobic surface layer with a contact angle with water being 50° or higher. Next, form on the plasma-processed hydrophobic surface an organic film including a fluorinated aromatic carbon hydride polymer film.Type: ApplicationFiled: August 27, 2004Publication date: April 21, 2005Applicant: Semiconductor Leading Edge Technologies, Inc.Inventors: Naruhiko Kaji, Katsumi Yoneda
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Publication number: 20040188675Abstract: A semiconductor device comprises an inorganic film on a semiconductor substrate, an intermediate film on the inorganic film and containing silicon, and an organic film on the intermediate film and containing fluorine. The organic film is made of a fluorinated arylene film.Type: ApplicationFiled: March 9, 2004Publication date: September 30, 2004Applicant: Semiconductor Leading Edge Technologies, Inc.Inventor: Naruhiko Kaji
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Patent number: 6798038Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: GrantFiled: May 9, 2002Date of Patent: September 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Publication number: 20040173870Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: ApplicationFiled: March 15, 2004Publication date: September 9, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Publication number: 20040150075Abstract: A porous MSQ is formed on a silicon substrate, and an SiC mask is formed thereon. Plasma etching using the SiC mask as a mask is performed to form a trench in the porous MSQ. A fluorinated polyxylilene film is formed on the entire surface of the substrate 1 including the side surfaces of the trench, and the unnecessary fluorinated polyxylilene film formed on the area other than the side surfaces of the trench is removed. A barrier-metal film and a seed Cu layer are formed in the trench and a Cu is deposited.Type: ApplicationFiled: December 16, 2003Publication date: August 5, 2004Applicant: Semiconductor Leading Edge Technologies, Inc.Inventor: Naruhiko Kaji
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Publication number: 20030052384Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: ApplicationFiled: May 9, 2002Publication date: March 20, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Publication number: 20020134429Abstract: A gas-circulating processing apparatus which comprises a processing chamber, a gas feeding piping, a gas supply piping, a first exhaust mechanism discharging a gas from the processing chamber, a second exhaust mechanism discharging a portion of a gas discharged from the first exhaust mechanism, a back pressure adjusting mechanism interposed between the first exhaust mechanism and the second exhaust mechanism to adjust a back pressure of the first exhaust mechanism, and a gas circulating piping which is configured to combine another portion of the gas that has been discharged from the first exhaust mechanism with a processing gas supplied from the gas supply piping, wherein the gas feeding piping has a larger inner diameter than that of the gas supply, or the processing gas is introduced into the first exhaust mechanism, or a first heater is provided to heat at least part of the circulating route.Type: ApplicationFiled: December 27, 2001Publication date: September 26, 2002Inventors: Hiroshi Kubota, Rempei Nakata, Naruhiko Kaji, Itsuko Sakai, Takashi Yoda
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Patent number: 6368977Abstract: There is provided a semiconductor device manufacturing method that comprises a first step of loading a processed substrate in a reaction chamber, a second step of introducing a reaction gas into the reaction chamber at a predetermined flow rate, a third step of maintaining an interior of the reaction chamber at a predetermined pressure, a fourth step of starting generation of plasma by supplying a high frequency power to an electrode arranged in the reaction chamber, a fifth step of applying a predetermined process to the processed substrate, and a sixth step of stopping generation of the plasma by stopping supply of the high frequency power after the predetermined process is completed, wherein the reaction gas is introduced continuously when the generation of the plasma is stopped.Type: GrantFiled: June 29, 2000Date of Patent: April 9, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Narita, Yukimasa Yoshida, Katsuaki Aoki, Hiroshi Fujita, Takashi O, Toshimitsu Omine, Isao Matsui, Osamu Yamazaki, Naruhiko Kaji
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Patent number: 6164295Abstract: There is provided a CVD apparatus and a cleaning method which can precisely perform cleaning at a high speed, in order to increase the throughput of a CVD apparatus. A film formation gas (e.g., SiH.sub.4 and O.sub.2 gases) is introduced from a source gas supply pipe into a chamber to form a silicon oxide film (SiO.sub.2) on a wafer placed on a susceptor by using a plasma or the like. A thin film (SiO.sub.2) mainly consisting of silicon and oxygen, an imperfect oxide film of silicon, or the like also attaches to a wall surface and the respective surfaces of a window plate, a vacuum seal portion, the susceptor, an electrode, an insulator, an exhaust pipe, and the like in the chamber. An HF-based gas supply system for a cleaning etching gas is arranged to clean the interior of the chamber of the CVD apparatus. Particularly, a film formed with a source gas of Si.sub.x H.sub.2x+2 (x=1, 2, 3) and O.sub.2 is more perfect than an imperfect oxide film (e.g.Type: GrantFiled: April 29, 1997Date of Patent: December 26, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Akio Ui, Naruhiko Kaji, Hideshi Miyajima, Nobuo Hayasaka
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Patent number: 6153509Abstract: In a method of manufacturing a semiconductor device including a semiconductor element formed on a semiconductor substrate, an SiOF film is formed at least on the top surfaces of metal wirings under condition that an in-chamber pressure is 5 mTorr or lower. The SiOF film can thus be buried into a space between the metal wirings without causing any void and the capacitance between the wirings can be prevented from increasing, while preventing the metal wirings from being damaged and preventing the aspect ratio from increasing.Type: GrantFiled: June 30, 1999Date of Patent: November 28, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kei Watanabe, Yukio Nishiyama, Naruhiko Kaji, Hideshi Miyajima
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Patent number: 5792326Abstract: Ozonizer (10) which supplies a feed gas to ozone generating cell (11) under application of a high voltage and which delivers an ozone gas through an ozone gas transport path (consisting of pipes (14) and (15)) as it has been generated in said ozone generating cell (11) is characterized in that the ozone gas transport path is furnished with means for removing at least one of NOx, HF and SOx (in the drawings, the means is for removing NOx) and that the ozone gas from the ozone generating cell (11) is passed through said removing means, whereby at least one of NOx, HF and SOx in said ozone gas is removed before it is delivered to a subsequent stage. The product ozone is not contaminated with Cr compounds at all or insufficiently contaminated to cause any practical problems in the fabrication of highly integrated semiconductor devices.Type: GrantFiled: January 13, 1997Date of Patent: August 11, 1998Inventors: Minoru Harada, Ryoichi Shinjo, Manabu Tsujimura, Rempei Nakata, Kunihiro Miyazaki, Naruhiko Kaji, Yutaka Nakano
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Patent number: 5794114Abstract: In an improved ozonizer, at least those parts of an ozone gas delivery path located downstream of an ozone generating cell which are to come into contact with ozone gas are either composed of or coated with at least one ozone-resistant, Cr-free material selected from among aluminum (Al), an aluminum alloy, Teflon, fluorinated nickel, a nickel alloy, a silicon oxide based glass and a high-purity aluminium oxide. The ozonizer is capable of producing ozone that is not contaminated with Cr compounds at all or which is insufficiently contaminated to cause any practical problem in the fabrication of highly integrated semiconductor devices.Type: GrantFiled: August 23, 1995Date of Patent: August 11, 1998Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Minoru Harada, Ryoichi Shinjo, Manabu Tsujimura, Rempei Nakata, Kunihiro Miyazaki, Naruhiko Kaji
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Patent number: 5702673Abstract: An ozone generating apparatus produces highly pure ozone gas which can be used in a semiconductor manufacturing process. The ozone generating apparatus comprises a high voltage source, an ozone generating cell which generates ozone gas by supplying a material gas while applying a high voltage from the high voltage source, and a passage for delivering the generated ozone gas from the ozone generating cell to a desired location. The passage comprises a material which has a passivation film formed by a passivation treatment in a dry process. The oxide passivation film comprises chromium oxide film, iron oxide film or a composite film of chromium oxide and iron oxide.Type: GrantFiled: April 17, 1996Date of Patent: December 30, 1997Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Naruhiko Kaji, Yutaka Nakano, Rempei Nakata, Minoru Harada, Ryoichi Shinjo, Manabu Tsujimura
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Patent number: 5632868Abstract: Ozonizer (10) which supplies a feed gas to ozone generating cell (11) under application of a high voltage and which delivers an ozone gas through an ozone gas transport path (consisting of pipes (14) and (15)) as it has been generated in said ozone generating cell (11) is characterized in that the ozone gas transport path is furnished with means for removing at least one of NOx, HF and SOx (in the drawings, the means is for removing NOx) and that the ozone gas from the ozone generating cell (11) is passed through said removing means, whereby at least one of NOx, HF and SOx in said ozone gas is removed before it is delivered to a subsequent stage. The product ozone is not contaminated with Cr compounds at all or insufficiently contaminated to cause any practical problems in the fabrication of highly integrated semiconductor devices.Type: GrantFiled: August 23, 1995Date of Patent: May 27, 1997Assignee: Ebara CorporationInventors: Minoru Harada, Ryoichi Shinjo, Manabu Tsujimura, Rempei Nakata, Kunihiro Miyazaki, Naruhiko Kaji, Yutaka Nakano
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Patent number: 5571578Abstract: A plasma CVD device having a chamber, an upper electrode provided in the chamber, an under electrode provided in the chamber to be opposite to the upper electrode and to mount a sample thereon, and a plurality of power sources having a different frequency connected to the upper electrode. Gas is introduced into the chamber of the plasma CVD device, the gas contains at least an organic silicon compound, CF.sub.4 and O.sub.2, and has an element ratio (F/Si) of silicon (Si), constituting the organic silicon compound, to fluorine (F), constituting CF.sub.4, to be set to 15 or more. Si(OC.sub.2 H.sub.5).sub.4 or Si(OCH.sub.3).sub.4 is used as an organic silicon compound.Type: GrantFiled: January 13, 1995Date of Patent: November 5, 1996Assignee: Kabushiki Kaisha TohsibaInventors: Naruhiko Kaji, Riichirou Aoki, Hiroyuki Toyama, Hidemitsu Egawa, Takamitsu Yoshida, Yukio Nishiyama