Patents by Inventor Narumasa Soejima
Narumasa Soejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9899469Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.Type: GrantFiled: December 11, 2015Date of Patent: February 20, 2018Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Shinya Nishimura, Hirokazu Fujiwara, Narumasa Soejima, Yuichi Takeuchi
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Patent number: 9853139Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.Type: GrantFiled: February 10, 2015Date of Patent: December 26, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Toshimasa Yamamoto, Narumasa Soejima
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Patent number: 9818860Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.Type: GrantFiled: November 30, 2016Date of Patent: November 14, 2017Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
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Publication number: 20170317162Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.Type: ApplicationFiled: December 11, 2015Publication date: November 2, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Shinya NISHIMURA, Hirokazu FUJIWARA, Narumasa SOEJIMA, Yuichi TAKEUCHI
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Patent number: 9793376Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.Type: GrantFiled: August 6, 2013Date of Patent: October 17, 2017Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shinichiro Miyahara, Toshimasa Yamamoto, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
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Patent number: 9779906Abstract: An electron emission device includes a substrate and an electron emission layer. The electron emission layer is provided above the substrate, and is provided with an opening. The electron emission layer has an edge defining the opening and is configured to emit electrons from the edge when the edge is irradiated with light.Type: GrantFiled: October 2, 2015Date of Patent: October 3, 2017Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHOInventors: Tsuyoshi Ishikawa, Takashi Katsuno, Narumasa Soejima
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Patent number: 9773883Abstract: A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.Type: GrantFiled: October 6, 2014Date of Patent: September 26, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Akitaka Soeno, Yuichi Takeuchi, Narumasa Soejima
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Publication number: 20170243712Abstract: An electron emission device includes a substrate and an electron emission layer. The electron emission layer is provided above the substrate, and is provided with an opening. The electron emission layer has an edge defining the opening and is configured to emit electrons from the edge when the edge is irradiated with light.Type: ApplicationFiled: October 2, 2015Publication date: August 24, 2017Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHOInventors: Tsuyoshi ISHIKAWA, Takashi KATSUNO, Narumasa SOEJIMA
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Patent number: 9735260Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.Type: GrantFiled: February 27, 2014Date of Patent: August 15, 2017Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tetsu Kachi, Yoshitaka Nakano, Tsutomu Uesugi, Hiroyuki Ueda, Narumasa Soejima
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Patent number: 9673288Abstract: In a silicon carbide semiconductor device, a p-type SiC layer is disposed in a corner of a bottom of a trench. Thus, even if an electric field is applied between a drain and a gate when a MOSFET is turned off, a depletion layer in a pn junction between the p-type SiC layer and an n? type drift layer greatly extends toward the n? type drift layer, and a high voltage caused by an influence of a drain voltage hardly enters a gate insulating film. Hence, an electric field concentration within the gate insulating film can be reduced, and the gate insulating film can be restricted from being broken. In this case, although the p-type SiC layer may be in a floating state, the p-type SiC layer is formed in only the corner of the bottom of the trench. Thus, the deterioration of the switching characteristic is relatively low.Type: GrantFiled: April 17, 2013Date of Patent: June 6, 2017Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuichi Takeuchi, Kazumi Chida, Narumasa Soejima, Yukihiko Watanabe
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Patent number: 9640655Abstract: A semiconductor device is provided with: a first conductivity type contact region; a second conductivity type body region; a first conductivity type drift region of; a trench formed through the contact region and body region from a front surface of the semiconductor substrate, wherein a bottom of the trench is positioned in the drift region; an insulating film covering an inner surface of the trench; a gate electrode accommodated in the trench in a state covered with the insulating film; and a second conductivity type floating region formed at a position deeper than the bottom of the trench, and adjacent to the bottom of the trench. The floating region includes a first layer adjacent to the bottom of the trench and a second layer formed at a position deeper than the first layer, wherein a width of the first layer is broader than a width of the second layer.Type: GrantFiled: January 24, 2013Date of Patent: May 2, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Shinya Nishimura, Narumasa Soejima, Kensaku Yamamoto
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Patent number: 9608104Abstract: A silicon carbide semiconductor device includes: a vertical MOSFET having: a semiconductor substrate including a high-concentration impurity layer and a drift layer; a base region; a source region; a trench gate structure; a source electrode; and a drain electrode. The base region has a high-concentration base region and a low-concentration base region having a second conductivity type with an impurity concentration lower than the high-concentration base region, which are stacked each other. Each of the high-concentration base region and the low-concentration base region contacts a side surface of the trench.Type: GrantFiled: May 28, 2014Date of Patent: March 28, 2017Assignee: DENSO CORPORATIONInventors: Yuichi Takeuchi, Naohiro Suzuki, Jun Morimoto, Narumasa Soejima
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Patent number: 9607836Abstract: A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.Type: GrantFiled: September 24, 2013Date of Patent: March 28, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu Fujiwara, Narumasa Soejima
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Publication number: 20170084735Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.Type: ApplicationFiled: November 30, 2016Publication date: March 23, 2017Inventors: Yuichi TAKEUCHI, Naohiro SUZUKI, Masahiro SUGIMOTO, Hidefumi TAKAYA, Akitaka SOENO, Jun MORIMOTO, Narumasa SOEJIMA, Yukihiko WATANABE
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Publication number: 20170018643Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.Type: ApplicationFiled: February 10, 2015Publication date: January 19, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Hidefumi TAKAYA, Jun SAITO, Akitaka SOENO, Toshimasa YAMAMOTO, Narumasa SOEJIMA
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Publication number: 20170012136Abstract: A terminal structure includes: a first trench extending along a depth direction from an upper surface of a semiconductor substrate; a plurality of second trenches, each of which extends along the depth direction from a bottom surface of the first trench and which are arranged at intervals in a direction away from an element portion; a plurality of first floating regions having a floating potential, each of which is exposed at the bottom surface of the first trench, is disposed between the second trenches, and forms a PN-junction with a surrounding region thereof; and a plurality of second floating regions having a floating potential, each of which is exposed at a bottom surface of the second trench and forms a PN-junction with a surrounding region thereof. The plurality of second floating regions is arranged to be separated from each other in the direction away from the element portion.Type: ApplicationFiled: July 5, 2016Publication date: January 12, 2017Inventors: Yosuke Maegawa, Shinichiro Miyahara, Narumasa Soejima
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Patent number: 9543428Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.Type: GrantFiled: June 6, 2013Date of Patent: January 10, 2017Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuichi Takeuchi, Naohiro Suzuki, Masahiro Sugimoto, Hidefumi Takaya, Akitaka Soeno, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
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Patent number: 9515160Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.Type: GrantFiled: January 20, 2016Date of Patent: December 6, 2016Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuichi Takeuchi, Kazumi Chida, Narumasa Soejima, Yukihiko Watanabe
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Publication number: 20160351680Abstract: A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.Type: ApplicationFiled: October 6, 2014Publication date: December 1, 2016Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Akitaka SOENO, Yuichi TAKEUCHI, Narumasa SOEJIMA
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Publication number: 20160163818Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.Type: ApplicationFiled: January 20, 2016Publication date: June 9, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuichi TAKEUCHI, Kazumi CHIDA, Narumasa SOEJIMA, Yukihiko WATANABE