Abstract: Techniques for sensor data time alignment are described. According to one or more embodiments, sensor data from different sensor systems is time-aligned to a reference time base. For instance, reference time values may be propagated to sensor systems to enable the sensor systems to mark sensor data based on the reference time values. Sensor data from a sensor system may be time-aligned by applying an alignment policy to the sensor data. An alignment policy, for example, accounts for a difference between a time base of a sensor system and a reference time base. Thus, sensor data from different sensor systems may be aligned to common time values in a variety of different ways.

Abstract: Embodiments discussed herein enable sensor selection based on context and policy to provide for a variety of different sensor types and configurations, and for detecting a variety of different phenomena. In at least some embodiments, a sensor hub is employed to receive requests for sensor data from various functionalities and to select sensors to provide the sensor data based on application of context to policies that specify parameters for sensor selection.

Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues data transfer requests. The transfer controller includes separate control of data source and data destination in a data transfer corresponding to the data transfer requests. The transfer controller includes a data transfer program register and active source and destination registers. The transfer controller operates from the active source and destination registers. Upon completion of a data transfer the transfer controller writes data transfer parameters from the data transfer program register to the active source and destination registers.

Abstract: A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.

Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.

Abstract: The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.