Patents by Inventor Natarajan Viswanathan
Natarajan Viswanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11645441Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.Type: GrantFiled: December 31, 2020Date of Patent: May 9, 2023Assignee: Cadence Design Systems, Inc.Inventors: Bentian Jiang, Natarajan Viswanathan, Zhuo Li, Yi-Xiao Ding
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Patent number: 11625525Abstract: Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.Type: GrantFiled: May 7, 2021Date of Patent: April 11, 2023Assignee: Cadence Design Systems, Inc.Inventors: Zhuo Li, Natarajan Viswanathan, Vitor Bandeira, Yi-Xiao Ding
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Patent number: 11244099Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.Type: GrantFiled: December 31, 2020Date of Patent: February 8, 2022Assignee: Cadence Design Systems, Inc.Inventors: Bentian Jiang, Natarajan Viswanathan, Zhuo Li, Yi-Xiao Ding
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Patent number: 11188702Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.Type: GrantFiled: December 31, 2020Date of Patent: November 30, 2021Assignee: Cadence Design Systems, Inc.Inventors: Bentian Jiang, Natarajan Viswanathan, William Robert Reece, Zhuo Li
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Patent number: 10963617Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.Type: GrantFiled: January 6, 2020Date of Patent: March 30, 2021Assignee: Cadence Design Systems, Inc.Inventors: Andrew Mark Chapman, William Robert Reece, Natarajan Viswanathan, Mehmet Can Yildiz, Gracieli Posser, Zhuo Li
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Patent number: 10685160Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.Type: GrantFiled: September 25, 2018Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Myung-Chul Kim, Shyam Ramji, Paul G. Villarrubia, Natarajan Viswanathan
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Patent number: 10402522Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.Type: GrantFiled: August 31, 2017Date of Patent: September 3, 2019Assignee: Cadence Design Systems, Inc.Inventors: Natarajan Viswanathan, Charles Jay Alpert, Thomas Andrew Newton, William Robert Reece
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Patent number: 10318693Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.Type: GrantFiled: August 29, 2017Date of Patent: June 11, 2019Assignee: Cadence Design Systems, Inc.Inventors: Natarajan Viswanathan, Zhuo Li, Charles Jay Alpert, William Robert Reece, Thomas Andrew Newton
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Patent number: 10289797Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.Type: GrantFiled: August 28, 2017Date of Patent: May 14, 2019Assignee: Cadence Design Systems, Inc.Inventors: Natarajan Viswanathan, Charles Jay Alpert, Wen-Hao Liu, Thomas Andrew Newton
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Publication number: 20190026418Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.Type: ApplicationFiled: September 25, 2018Publication date: January 24, 2019Inventors: Myung-Chul Kim, Shyam Ramji, Paul G. Villarrubia, Natarajan Viswanathan
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Patent number: 10140409Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.Type: GrantFiled: August 11, 2016Date of Patent: November 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Myung-Chul Kim, Shyam Ramji, Paul G. Villarrubia, Natarajan Viswanathan
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Patent number: 9870097Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.Type: GrantFiled: June 30, 2016Date of Patent: January 16, 2018Assignee: QUALCOMM IncorporatedInventors: Ashutosh Ravindra Joharapurkar, Jean CauXuan Le, Natarajan Viswanathan, Patrick Yin Chan
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Publication number: 20170220722Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.Type: ApplicationFiled: August 11, 2016Publication date: August 3, 2017Inventors: MYUNG-CHUL KIM, SHYAM RAMJI, PAUL G. VILLARRUBIA, NATARAJAN VISWANATHAN
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Patent number: 9524363Abstract: An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.Type: GrantFiled: May 31, 2012Date of Patent: December 20, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Charles J. Alpert, Gi-Joon Nam, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan
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Patent number: 9495501Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.Type: GrantFiled: January 29, 2016Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Myung-Chul Kim, Shyam Ramji, Paul G. Villarrubia, Natarajan Viswanathan
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Publication number: 20160313863Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.Type: ApplicationFiled: June 30, 2016Publication date: October 27, 2016Inventors: Ashutosh Ravindra Joharapurkar, Jean CauXuan Le, Natarajan Viswanathan, Patrick Yin Chan
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Publication number: 20160291797Abstract: Random sampling techniques include techniques for reducing or eliminating errors in the output of capacitive sensor arrays such as touch panels. The channels of the touch panel are periodically sampled to determine the presence of one or more touch events. Each channel is individually sampled in a round robin fashion, referred to as a sampling cycle. During each sampling cycle, all channels are sampled once. Multiple sampling cycles are performed such that each channel is sampled multiple times. Random sampling techniques are used to sample each of the channels. One random sampling technique randomizes a starting channel in each sampling cycle. Another random sampling technique randomizes the selection of all channels in each sampling cycle. Yet another random sampling technique randomizes the sampling cycle delay period between each sampling cycle. Still another random sampling technique randomizes the channel delay period between sampling each channel.Type: ApplicationFiled: June 7, 2016Publication date: October 6, 2016Inventors: Ashutosh Ravindra Joharapurkar, Patrick Yin Chan, David Allen, Natarajan Viswanathan
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Patent number: 9442610Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.Type: GrantFiled: July 3, 2013Date of Patent: September 13, 2016Assignee: QUALCOMM Technologies, Inc.Inventors: Ashutosh R. Joharapurkar, Jean C. Le, Natarajan Viswanathan, Patrick Chan
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Publication number: 20160209947Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.Type: ApplicationFiled: July 3, 2013Publication date: July 21, 2016Inventors: Ashutosh R. Joharapurkar, Jean C. Le, Natarajan Viswanathan, Patrick Chan
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Patent number: 9391607Abstract: Random sampling techniques include techniques for reducing or eliminating errors in the output of capacitive sensor arrays such as touch panels. The channels of the touch panel are periodically sampled to determine the presence of one or more touch events. Each channel is individually sampled in a round robin fashion, referred to as a sampling cycle. During each sampling cycle, all channels are sampled once. Multiple sampling cycles are performed such that each channel is sampled multiple times. Random sampling techniques are used to sample each of the channels. One random sampling technique randomizes a starting channel in each sampling cycle. Another random sampling technique randomizes the selection of all channels in each sampling cycle. Yet another random sampling technique randomizes the sampling cycle delay period between each sampling cycle. Still another random sampling technique randomizes the channel delay period between sampling each channel.Type: GrantFiled: January 7, 2011Date of Patent: July 12, 2016Assignee: QUALCOMM Technologies, Inc.Inventors: Ashutosh Ravindra Joharapurkar, Patrick Chan, David L. Allen, Natarajan Viswanathan