Patents by Inventor Nathalie Messina
Nathalie Messina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110075306Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.Type: ApplicationFiled: December 9, 2010Publication date: March 31, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yves Leduc, Nathalie Messina, Charvaka Duvvury, Kurt P. Wachtler
-
Patent number: 7916808Abstract: A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine and cosine responses that are stored in a ROM (read-only memory) or other memory structure. The modulator output is then calculated as a simple sum of values read from the ROM and controlled by the input burst data stream.Type: GrantFiled: December 22, 2006Date of Patent: March 29, 2011Assignee: Texas Instruments IncorporatedInventors: Peter Considine, Nathalie Messina, Jean-Christophe Jiguet
-
Patent number: 7872841Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.Type: GrantFiled: March 17, 2008Date of Patent: January 18, 2011Assignee: Texas Instruments IncorporatedInventors: Yves Leduc, Nathalie Messina, Charvaka Duvvury, Kurt P. Wachtler
-
Publication number: 20090020313Abstract: A system comprising a first layer comprising one or more metal sub-layers and a protective overcoat (PO) layer adjacent to the first layer. The PO layer is adapted to protect the first layer, and a circuit logic is at least partially embedded within the PO layer. The circuit logic couples to one of the metal sub-layers.Type: ApplicationFiled: July 20, 2007Publication date: January 22, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yves LEDUC, Nathalie MESSINA, Kelly J. TAYLOR, Louis N. HUTTER, Jeffrey P. SMITH, Byron L. WILLIAMS, Abha R. SINGH, Scott R. SUMMERFELT, Daniel L. CALLAHAN
-
Publication number: 20080278873Abstract: A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.Type: ApplicationFiled: March 17, 2008Publication date: November 13, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yves Leduc, Nathalie Messina, Charvaka Duvvury, Kurt P. Wachtler
-
Publication number: 20070160166Abstract: A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine and cosine responses that are stored in a ROM (read-only memory) or other memory structure. The modulator output is then calculated as a simple sum of values read from the ROM and controlled by the input burst data stream.Type: ApplicationFiled: December 22, 2006Publication date: July 12, 2007Inventors: Peter Considine, Nathalie Messina, Jean-Christophe Jiguet
-
Patent number: 6960946Abstract: A CMOS bus receiver for converting a reduced voltage swing input signal at an input node to a higher voltage swing output signal at an output node. The receiver includes a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node. A third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node are also provided, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors.Type: GrantFiled: June 3, 2004Date of Patent: November 1, 2005Assignee: Texas Instruments IncorporatedInventors: Nathalie Messina, Yves Leduc
-
Publication number: 20050077945Abstract: A CMOS bus receiver for converting a reduced voltage swing input signal at an input node to a higher voltage swing output signal at an output node. The receiver includes a first and a second MOS transistor connected in series by their source and drain between a first side and a second side of a power supply, a gate of the first MOS transistor being connected to the input node, the common connection node of the first and second MOS transistors being connected to the output node. A third and a fourth MOS transistor connected in series by their source and drain between the first side of the power supply and the input node are also provided, a gate of the third MOS transistor being connected to the output node, and a gate of the second MOS transistor being connected to the common connection node of the third and fourth MOS transistors.Type: ApplicationFiled: June 3, 2004Publication date: April 14, 2005Inventors: Nathalie Messina, Yves Leduc
-
Publication number: 20040215856Abstract: A bus (10) uses DS encoding with an additional wire framing the signal on the Data and Strobe lines, allocating control of the lines by a master (12) or a selected slave (14). A data clock can be recovered from the Data and Strobe lines, eliminating clock skew between circuits. Slaves (14) with differing speed abilities are supported by generating an address portion of the message at a first speed and the remaining transaction portion at the full capabilities of the selected slave. Further, the slaves (14) can adapt their bus drivers to various voltage levels to accommodate master circuits using different processing technologies. The bus (10) is scalable to allow high bandwidths.Type: ApplicationFiled: November 5, 2003Publication date: October 28, 2004Inventors: Yves Leduc, Nathalie Messina, Gael Christian Clave