Patents by Inventor Nathan L. Yao

Nathan L. Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Instruction queue scanning using opcode identification
    Patent number: 5896518
    Abstract: A superscalar complex instruction set computer ("CISC") processor (100) having a reduced instruction set computer ("RISC") superscalar core (110) includes an instruction cache (104) which identifies and marks raw x86 instruction start and end points and encodes "pre-decode" information, a byte queue (106) which is a queue of aligned instruction and pre-decode information of the "predicted executed" state, and an instruction decoder (108) which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue. The instruction decoder includes in each dispatch position a logic-based conversion path, a memory-based conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer (400) directs x86 instructions from the byte queue to the conversion paths.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: April 20, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nathan L. Yao, Michael D. Goddard
  • Apparatus and method for instruction queue scanning
    Patent number: 5630082
    Abstract: A superscalar complex instruction set computer ("CISC") processor (100) having a reduced instruction set computer ("RISC") superscalar core (110) includes an instruction cache (104) which identifies and marks raw x86 instruction start and end points and encodes "pre-decode" information, a byte queue (106) which is a queue of aligned instruction and pre-decode information of the "predicted executed" state, and an instruction decoder (108) which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue. The instruction decoder includes in each dispatch position a logic-based conversion path, a memory-based conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer (400) directs x86 instructions from the byte queue to the conversion paths.
    Type: Grant
    Filed: August 18, 1994
    Date of Patent: May 13, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nathan L. Yao, Michael D. Goddard