Abstract: A capacitance measurement sensor, having a voltage subtractor that rejects common signals between the columns or rows of a touch sensor matrix depending on which are driven and which are being sensed, is described.

Abstract: A system and method for measuring capacitance of a capacitive sensor array is disclosed. Upon measuring the capacitance, position information with respect to the sensor array may be determined. A column, a first row, and a second row of a capacitive sensor array may be selected. The first row and the second row intersect with the column of the capacitive sensor array. A differential capacitance between the first row and the second row may be measured. The differential capacitance may be utilized in determining a location of an object proximate to the capacitive sensor array.

Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract: One embodiment includes a system configured to identify a preferred channel for radio communication from a plurality of consecutive integer frequencies including preferred channels and non-preferred channels, the system further to generate a plurality of radio channels corresponding to a plurality of consecutive integer frequencies based on a generation of reference frequencies, identifies preferred channels and non-preferred channels from the plurality of radio channels, where frequency synthesizer settling times of the preferred channels are faster than frequency synthesizer settling times of the non-preferred channels, scan the preferred channels for radio activity, select one of preferred channels responsive to the scanned radio activity; and utilize one of the reference frequencies to generate a radio frequency corresponding to the selected one of the preferred channels.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: A system and method of loading a programmable counter includes storing a first digital divide value in a register. The first digital divide value is then loaded from the register to a programmable counter. The method further includes writing a second digital divide value to the register at a time responsive to a time remaining to complete a counting cycle of the programmable counter.

Abstract: An improved circuit and method is described herein for extending the usable frequency range of a high performance, narrow band phase locked loop (PLL) device. For example, the improved circuit and method may perform a calibration sequence for calibrating an LC-type voltage controlled oscillator (VCO) immediately before or during operation of the PLL device. Unlike previous methods, the calibration sequence described herein provides a fast and convenient method for extending the usable frequency range of a PLL by shifting the center frequency of the LC-type VCO to a desired frequency. For example, the VCO center frequency may be incrementally shifted (e.g., either high or low) to compensate for the actual environmental conditions in which the PLL is used (i.e., to compensate for specific process, voltage, and temperature conditions).

Abstract: A method and apparatus to synchronize a boost signal. The apparatus includes a boost circuit and a synchronization circuit. The synchronization circuit is coupled to the boost circuit. The boost circuit generates an unsynchronized boost signal to boost a voltage signal from a first voltage to a second voltage. The synchronization circuit synchronizes the unsynchronized boost signal with a reference signal to generate a synchronized boost signal.

Abstract: A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a calibration input, and a clock signal output; and a logic circuit for dynamically calibrating an operating frequency of the phase locked loop during operation of the phase locked loop. In one embodiment, the logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is lower than the reference voltage, the logic circuit decreases the operating frequency of the phase locked loop circuit. The logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is higher than the reference voltage, the logic circuit increases the operating frequency of the phase locked loop circuit.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract: The present invention adds an additional feedback loop to a phase locked loop (PLL). The additional feedback loop detects if the actual output frequency of the PLL is above or below the desired output frequency. If the actual output frequency is above the desired output frequency a signal is added to the forward path of the PLL to decrease the frequency of the PLL oscillator. If the actual output frequency is below the desired output frequency a signal is added to the forward path of the PLL to increase the frequency of the PLL oscillator.

Abstract: A Phase Locked Loop (PLL) that has a substantially constant gain over a wide frequency range. The frequency range over which the PLL operates is divided into a number of frequency sub-ranges. The circuit includes a mechanism for adjusting the loop gain profile as the PLL moves from one frequency sub-range to another. When the PLL switches to a new frequency sub-range, the loop gain profile is adjusted to a pre-established value. Changes of frequency within each sub-range are then accomplished with the loop gain varying within a pre-established range.

Abstract: Method and system for controllably and sequentially powering up subsystems of an electronic system, device or integrated circuit. In one example, a first supply voltage is selectively applied to a first subsystem, and when the first supply voltage has reached a predetermined value, a second supply voltage is selectively applied to the second subsystem. The first and second supply voltages may also be boosted to provide fast startup timing. In this manner, the first subsystem is powered-up before the second supply voltage is applied to the second subsystem—this provides for controlled, sequential power up of the subsystems of the electronic system, device or integrated circuit.

Abstract: A phase frequency detector (PFD) utilizes hysteresis dead zone avoidance while maximizing the linear range and minimizing the power and area consumed by the PFD circuit. The PFD includes a hysteresis in a reset logic gate, which prevents the reset logic gate from switching its output before each of the corrective pulses from the PFD reach final steady state DC voltage values. The PFD response simulates an ideal response, such that linearity is maintained at the phase lock point and throughout a linear range of +/−2&pgr;. In addition, the hysteresis reset logic gate monitors the corrective pulses to insert an appropriate amount of time delay into the PFD reset path without introducing additional delay elements. As a result, the linear range of the PHD is maximized and the power and area consumed by the PFD is minimized, due to the fact that additional delay elements are eliminated from the design.

Abstract: A method and circuit for reducing the power up time of a phase lock loop (PLL). In one embodiment, the present invention cuts off a first voltage to the phase lock loop thereby powering down the phase lock loop. In power down, a second voltage is utilized to maintain the power requirements of the filter node within the phase lock loop while the other components of the phase lock loop are powered down. The PLL is now in a power down mode. The present invention then restores the first voltage to the PLL. Once the internal components of the PLL stabilize, the second voltage is disengaged from the filter node wherein the phase lock loop is powered up to operational power.