Patents by Inventor Nathan S. Miller

Nathan S. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240156467
    Abstract: A compression device is used to increase intra-luminal pressure within the upper esophageal sphincter of a patient in order relieve an impact of an abnormal or defective upper esophageal sphincter anatomy, physiology, or functionality. In one implementation, the compression device is used in conjunction with an external pressure sensing device to determine the external pressure that is to be applied to the cricoid for a specific patient. The compression device can be a means for the management and/or treatment of abnormal upper esophageal sphincter functionality, or a means for strengthening an esophageal sphincter of a subject, or a means for curing esophageal reflux disease of a subject, or a means for improving vocal function in a subject, or a means for managing lung aspiration, or a means for applying cricoid pressure during anesthesia intubation, or a means for stabilizing body structures such as during medical imaging or radiation treatment.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 16, 2024
    Applicant: The Medical College of Wisconsin, Inc.
    Inventors: Nick T. Maris, James S. Miller, Reza Shaker, Timothy Bachman, Nathan Schlueter, Eugene Paul Maloney, Eric David North, Paul Raine, Peter Alex
  • Patent number: 11172016
    Abstract: A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Karl P. Brummel, Charles A. Giefer, Nathan S. Miller, Keith D. Underwood
  • Patent number: 10505848
    Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
  • Publication number: 20180287904
    Abstract: A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Karl P. Brummel, Charles A. Giefer, Nathan S. Miller, Keith D. Underwood
  • Publication number: 20170187637
    Abstract: In an embodiment, an out-of-order, reliable, end-to-end protocol is provided that can enable direct user-level data placement and atomic operations between nodes of a multi-node network. The protocol may be optimized for low-loss environments such as High Performance Computing (HPC) applications, and may enable loss detection and de-duplication of packets through the use of a robust window state manager at a target node. A multi-node network implementing the protocol may have increased system reliability, packet throughput, and increased tolerance for adaptively routed traffic, while still allowing atomic operations to be idempotently applied directly to a user memory location.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: Keith D. UNDERWOOD, Charles A. GIEFER, Mark DEBBAGE, Karl P. BRUMMEL, Nathan S. MILLER, Bruce M. PIRIE
  • Publication number: 20170187630
    Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
  • Publication number: 20130269078
    Abstract: Aspects for supporting a turndown shirt collar are disclosed. In a particular aspect, a semi-rigid shapeable device includes a rear region that forms a substantially semi-circle shape having a first and second end. For this particular embodiment, each of a first terminal end and a second terminal end are respectively oriented upwards and inwards relative to the rear region via a first bend at the first end and a second bend at the second end. In another aspect, a method that facilitates forming a shirt collar support is provided, which includes shaping a semi-rigid shapeable device into a substantially semi-circle shape. In a further aspect, a turndown collared shirt is provided, which includes a collar band comprising at least one collar sleeve configured to hold a shaping device.
    Type: Application
    Filed: April 14, 2012
    Publication date: October 17, 2013
    Inventors: Jason Andrade, Lawrence Garcia, Nathan S. Miller, Thomas Miller