Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

Abstract: Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

Abstract: Apparatuses and methods related to implementing refresh and access modes for memory. The refresh and access modes can be used to configure a portion of memory. The portions of memory can correspond to protected regions of memory. The refresh and access modes can influence the security level of data stored in the protected regions of memory.

Abstract: A memory device can be operated with a set of refresh control features. A host can access the memory device to discover the set of refresh control features. The host can command the memory device to change at least one of the set of refresh control features. The memory device can be operated with the original and/or changed set of refresh control features.

Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Memory with partial array density security is disclosed herein. In one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. The plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. Sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. To write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. The apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.

Abstract: Methods, systems, and devices for illegal operation reaction are described. A memory device may receive one or more commands to perform one or more respective access operations on an array of memory cells. A first circuit of the memory device may determine that the one or more commands would violate one or more thresholds associated with operation of the memory device, such as a timing threshold. In some cases, the first circuit may compare the one or more commands to the one or more patterns of commands stored at the memory device. A second circuit of the memory device may erase one or more memory cells of the memory device based on determining that the one or more thresholds associated with operation of the memory device would be violated, based on comparing the set of commands to the one or more patterns, or a combination thereof.

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Abstract: Methods, systems, and devices for illegal operation reaction are described. A memory device may receive one or more commands to perform one or more respective access operations on an array of memory cells. A first circuit of the memory device may determine that the one or more commands would violate one or more thresholds associated with operation of the memory device, such as a timing threshold. In some cases, the first circuit may compare the one or more commands to the one or more patterns of commands stored at the memory device. A second circuit of the memory device may erase one or more memory cells of the memory device based on determining that the one or more thresholds associated with operation of the memory device would be violated, based on comparing the set of commands to the one or more patterns, or a combination thereof.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

Abstract: Apparatuses and methods related to implementing refresh and access modes for memory. The refresh and access modes can be used to configure a portion of memory. The portions of memory can correspond to protected regions of memory. The refresh and access modes can influence the security level of data stored in the protected regions of memory.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.