Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

Abstract: During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.

Abstract: Techniques for processing silicon germanium (SiGe) thin films to reduce surface roughness thereof are provided herein. In an aspect, a method is disclosed that includes depositing a silicon germanium (SiGe) material upon a surface of a substrate at or below about 450 degrees Celsius, the substrate having a plurality of CMOS devices therein and forming, from the deposited SiGe material, a SiGe material film, wherein the SiGe material film has a jagged surface comprising projections and indentations extended along a direction substantially perpendicular to the surface of the substrate. The method further includes performing a chemical mechanical planarization (CMP) process to the jagged surface of the SiGe material, and reducing variations between the projections and the indentions along the direction substantially perpendicular to the surface of the substrate, and transforming the jagged surface of the SiGe material into a relatively smooth surface, compared to the jagged surface.

Abstract: A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring structure is formed overlying the first dielectric material. The method forms one or more first structure comprising a junction material overlying the first wiring structure. A second structure comprising a stack of material is formed overlying the first structure. The second structure includes a resistive switching material, an active conductive material overlying the resistive switching material, and a second wiring material overlying the active conductive material. The second structure is configured such that the resistive switching material is free from a coincident vertical sidewall region with the junction material.

Abstract: A system for treating a vascular condition includes a catheter having an inner member and an outer member, the outer member concentrically arranged about the inner member and a retractable drug delivery device disposed at a distal end of the inner member. A coating disposed on at least a portion of an outer surface of the retractable drug delivery device includes at least one therapeutic agent.

Abstract: Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.

Abstract: A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first wiring structure overlies the first dielectric material. The method forms a first electrode material overlying the first wiring structure and a resistive switching material comprising overlying the first electrode material. An active metal material is formed overlying the resistive switching material. The active metal material is configured to form an active metal region in the resistive switching material upon application of a thermal energy characterized by a temperature no less than about 100 Degree Celsius. In a specific embodiment, the method forms a blocking material interposing the active metal material and the resistive switching material to inhibit formation of the active metal region in the resistive switching material during the subsequent processing steps.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Abstract: A method for forming a non-volatile memory device includes providing a substrate having a surface region, forming a first wiring structure overlying the surface region, depositing a first dielectric material overlying the first wiring structure, forming a via opening in the first dielectric material to expose a portion of the first wiring structure, while maintaining a portion of the first dielectric material, forming a layer of resistive switching material comprising silicon, within the via opening, forming a silver material overlying the layer of resistive switching material and the portion of the first dielectric material, forming a diffusion barrier layer overlying the silver material, and selectively removing a portion of the silver material and a portion of the diffusion barrier layer overlying the portion of the first dielectric material while maintaining a portion of the silver material and a portion of the diffusion barrier material overlying the layer of silicon material.

Abstract: A system for treating a vascular condition includes a catheter having an inner member and an outer member, the outer member concentrically arranged about the inner member and a retractable drug delivery device disposed at a distal end of the inner member. A coating disposed on at least a portion of an outer surface of the retractable drug delivery device includes at least one therapeutic agent.

Abstract: The apparatus and methods of the present invention in a broad aspect provide novel multiple bioactive agent eluting stents for treating vascular diseases and conditions. Controlled elution of bioactive agents is achieved by the presence of the bioactive agents themselves. One or more characteristics of the bioactive agents cause variations in elution rates or profiles or the other bioactive agents.

Abstract: Disclosed herein are controlled release drug delivery systems. The systems comprise a medical device at least one nonoporous surface, at least one bioactive agent and optionally a biodegradable polymer. The nanoporous surfaces of the medical devices contain nanopores capable of acting as reservoirs for drugs that are controllably released.

Abstract: Described herein are implantable medical devices useful in treating vascular conditions such as restenosis. In one embodiment, stents are described in which a combination of bioactive agents is described for local delivery in the vasculature. The combination of bioactive agents comprises at least one compound capable of inhibiting smooth muscle cell proliferation and at least one compound capable of mitigating MCP- and/or TF induction. For example, a compound capable of inhibiting smooth muscle cell proliferation is a mTOR inhibitor and a compound capable of mitigating MCP-1 and/or TF induction is a corticosteroid.