Patents by Inventor Natsuki Kikuchi
Natsuki Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021805Abstract: The present disclosure provides primarily a negative electrode active material with reduced volume change during charge-discharge. The negative electrode active material of the disclosure consists of clathrate-type Si particles comprising one or more metals selected from the group consisting of Mo, Fe, Zn, Mg, Pd, Zr, Ag, Co, Cr, Nb and V. A negative electrode active material layer according to the disclosure comprises the negative electrode active material of the disclosure, and a lithium-ion battery of the disclosure comprises the negative electrode active material layer of the disclosure.Type: ApplicationFiled: July 12, 2023Publication date: January 18, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Mitsutoshi OTAKI, Jun YOSHIDA, Shinji NAKANISHI, Hisatsugu YAMASAKI, Natsuki KIKUCHI, Yasuhiro YAMAGUCHI, Tatsuya EGUCHI, Masanori HARATA, Kota URABE
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Publication number: 20220345553Abstract: An electronic device includes: a first electronic component; a cabinet provided facing the first electronic component; a second electronic component provided on a surface of the cabinet facing the first electronic component; and an adhesive sheet provided between the first electronic component and the cabinet and extending at least in a first direction. The adhesive sheet includes a widened portion surrounding the second electronic component, and a first narrowed portion adjacent to the widened portion in the first direction and provided with a tab for pulling the adhesive sheet. The widened portion is provided with a first opening penetrating the adhesive sheet and exposing the second electronic component to a side of the first electronic component. A longitudinal direction of the first opening is inclined with respect to the first direction toward the first narrowed portion to approach a connecting portion between the widened portion and the first narrowed portion.Type: ApplicationFiled: March 22, 2022Publication date: October 27, 2022Inventor: Natsuki KIKUCHI
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Publication number: 20220345551Abstract: An electronic devices includes: an electronic component; a cabinet provided facing the electronic component, an adhesive sheet including two extending portions extending along two adjacent sides of the electronic component and a curved portion connecting the two extending portions, and being provided between the electronic component and the cabinet; and a tab provided in one of the two extending portions, and configured to enable the adhesive sheet to be pulled. The adhesive sheet has a notched portion provided on a side of the one of the extending portions closer to the curved portion and one side in a width direction of the adhesive sheet.Type: ApplicationFiled: March 22, 2022Publication date: October 27, 2022Inventor: Natsuki KIKUCHI
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Patent number: 9711526Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar part. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The columnar part includes a semiconductor pillar provided in the stacked body and extending in a stacking direction of the stacked body, and a memory film provided between the semiconductor pillar and the stacked body. The electrode films include a first portion provided on a side part of the columnar part, a second part contacting the first portion and provided further outside the columnar part, and a first conductive layer covering an upper surface and a lower surface of the first portion.Type: GrantFiled: February 19, 2016Date of Patent: July 18, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kotaro Noda, Natsuki Kikuchi, Masaru Kito
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Publication number: 20170148806Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar part. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The columnar part includes a semiconductor pillar provided in the stacked body and extending in a stacking direction of the stacked body, and a memory film provided between the semiconductor pillar and the stacked body. The electrode films include a first portion provided on a side part of the columnar part, a second part contacting the first portion and provided further outside the columnar part, and a first conductive layer covering an upper surface and a lower surface of the first portion.Type: ApplicationFiled: February 19, 2016Publication date: May 25, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kotaro NODA, Natsuki KIKUCHI, Masaru KITO
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Patent number: 8675388Abstract: A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.Type: GrantFiled: September 15, 2011Date of Patent: March 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoichi Minemura, Takayuki Tsukamoto, Takafumi Shimotori, Hiroshi Kanno, Natsuki Kikuchi, Mitsuru Sato
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Patent number: 8274822Abstract: According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.Type: GrantFiled: February 1, 2011Date of Patent: September 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Tsukamoto, Yoichi Minemura, Natsuki Kikuchi, Mitsuru Sato, Hiroshi Kanno, Takafumi Shimotori
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Publication number: 20120069627Abstract: A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.Type: ApplicationFiled: September 15, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoichi MINEMURA, Takayuki TSUKAMOTO, Takafumi SHIMOTORI, Hiroshi KANNO, Natsuki KIKUCHI, Mitsuru SATO
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Publication number: 20110286260Abstract: According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.Type: ApplicationFiled: February 1, 2011Publication date: November 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayuki TSUKAMOTO, Yoichi Minemura, Natsuki Kikuchi, Mitsuru Sato, Hiroshi Kanno, Takafumi Shimotori