Abstract: A data transmitter circuit includes a reception line for receiving a logic signal made of a first logic signal and a second logic signal as a logic level opposite to the first logic signal, and an output circuit connected to a power supply potential and a ground potential to output one of the power supply potential and the ground potential when the logic signal received from the reception line is the first logic signal and output charges insulated from the power supply potential and the ground potential when the logic signal is the second logic signal.

Abstract: A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

Abstract: A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

Abstract: An SRAM comprising a plurality of SRAM storage cells connected in a plurality of rows and columns. Each storage cell has four terminals. Two terminals provide power for the storage cell, and two terminals are data terminals used in reading and writing the storage cell. The data terminals are connected to first and second bit lines in the storage cell's column via coupling transistors that are controlled by word lines associated with the various rows, there being two such bit lines associated with each column. The memory includes a power system that maintains a first potential difference between the power terminals of a storage cell when the storage cell is being read and a second potential difference between the power terminals when the storage cell is being written. The absolute value of the second potential difference is less than the absolute value of the first potential difference. This arrangement reduces the swing in potential on the bit lines needed to write a storage cell.

Abstract: A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

Abstract: A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a first node, and a plurality of capacitors for data storage connected at one end to the MOS transistors, respectively at the end remote from the node, and there is a predetermined regulation in relation of the capacitance of the capacitors.

Abstract: A digital signal is converted to an analog signal by an analog voltage generator. The analog signal is transferred via at least one analog signal line, to a digital voltage generator in which the analog signal transferred via the analog signal line is converted into a digital signal. In this way, the digital signal is converted to an analog signal at the input section of the semiconductor device, the converted analog signal is transferred to the digital signal generator through an analog signal line, and is converted back to a digital signal. Therefore, the number of wirings of the signal lines can be decreased, and hence the wiring occupying area on the semiconductor chip can be reduced.