Patents by Inventor Natsuki Sakaguchi
Natsuki Sakaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096413Abstract: A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.Type: ApplicationFiled: March 2, 2023Publication date: March 21, 2024Inventors: Natsuki SAKAGUCHI, Takashi MAEDA, Rieko FUNATSUKI, Hidehiro SHIGA
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Patent number: 9007845Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.Type: GrantFiled: June 19, 2014Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Natsuki Sakaguchi
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Patent number: 8917557Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, memory strings formed above the semiconductor substrate, and a control circuit configured to control voltages applied to the memory cells. In a read operation, when the control circuit precharges a first source line electrically connected to a selected memory string to a first voltage, the control circuit precharges a second source line electrically connected to an unselected memory string to a second voltage, the second voltage being higher than the first voltage, and after the second source line is precharged, the control circuit precharges a first bit line electrically connected to the selected memory string to the second voltage.Type: GrantFiled: December 14, 2012Date of Patent: December 23, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Natsuki Sakaguchi, Hiroshi Maejima
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Publication number: 20140301144Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Maejima, Natsuki Sakaguchi
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Publication number: 20140233320Abstract: A nonvolatile semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier that includes a first transistor having a first end electrically connected to the bit line, a second transistor electrically connected between a second end of the first transistor and ground, a third transistor electrically connected between a second end of the first transistor and a source line, and a controller configured to control the first, second, and third transistors after performing a program operation. After the program operation, the first and second transistors are turned on and then while the first transistor remains turned on, the second transistor is turned off and the third transistor is turned on.Type: ApplicationFiled: August 29, 2013Publication date: August 21, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Natsuki SAKAGUCHI, Hiroshi MAEJIMA
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Patent number: 8797801Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.Type: GrantFiled: August 20, 2013Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Natsuki Sakaguchi
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Publication number: 20130336062Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Natsuki Sakaguchi
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Patent number: 8542533Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.Type: GrantFiled: March 20, 2012Date of Patent: September 24, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Natsuki Sakaguchi
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Publication number: 20130155778Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, memory strings formed above the semiconductor substrate, and a control circuit configured to control voltages applied to the memory cells. In a read operation, when the control circuit precharges a first source line electrically connected to a selected memory string to a first voltage, the control circuit precharges a second source line electrically connected to an unselected memory string to a second voltage, the second voltage being higher than the first voltage, and after the second source line is precharged, the control circuit precharges a first bit line electrically connected to the selected memory string to the second voltage.Type: ApplicationFiled: December 14, 2012Publication date: June 20, 2013Inventors: Natsuki Sakaguchi, Hiroshi Maejima
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Publication number: 20120320678Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.Type: ApplicationFiled: March 20, 2012Publication date: December 20, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi MAEJIMA, Natsuki Sakaguchi