Abstract: A device to predict failure in a power supply includes a converter circuit configured to generate a regulated output voltage. The device additionally includes a first feedback circuit to generate a first feedback voltage proportional to the regulated output voltage and a second feedback circuit to generate a second feedback voltage based on the regulated output voltage. The second feedback circuit includes a voltage sampling circuit to detect the regulated output voltage, a correction circuit to generate a correction signal responsive to a voltage difference between the regulated output voltage and a specified output voltage, a reference circuit to obtain a specified correction signal to apply to the power supply, a comparator circuit to determine whether a difference between the generated correction signal and the specified correction signal exceeds a threshold signal value, and an alerting circuit to generate an alert signal responsive to the determination.

Abstract: A device to predict failure in a power supply includes a converter circuit configured to generate a regulated output voltage. The device additionally includes a first feedback circuit to generate a first feedback voltage proportional to the regulated output voltage and a second feedback circuit to generate a second feedback voltage based on the regulated output voltage. The second feedback circuit includes a voltage sampling circuit to detect the regulated output voltage, a correction circuit to generate a correction signal responsive to a voltage difference between the regulated output voltage and a specified output voltage, a reference circuit to obtain a specified correction signal to apply to the power supply, a comparator circuit to determine whether a difference between the generated correction signal and the specified correction signal exceeds a threshold signal value, and an alerting circuit to generate an alert signal responsive to the determination.

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

Abstract: A system comprises a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system; a plurality of power supply voltage sequencer devices electrically coupled to multiple power supplies of the plurality of power supplies, wherein a voltage sequencer device is configured to activate the multiple power supplies in a specified sequence; and a bus electrically coupled to the plurality of power supply voltage sequencer devices, wherein the bus is configured to communicate state information of the plurality of power supply voltage sequencer devices.

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

Abstract: A system comprises a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system; a plurality of power supply voltage sequencer devices electrically coupled to multiple power supplies of the plurality of power supplies, wherein a voltage sequencer device is configured to activate the multiple power supplies in a specified sequence; and a bus electrically coupled to the plurality of power supply voltage sequencer devices, wherein the bus is configured to communicate state information of the plurality of power supply voltage sequencer devices.

Abstract: A method and system for providing sensorless brushless DC motor control using predictive switch timing requires connecting a stator coil in a bridge configuration, applying a positive excitation voltage across the coil for a predetermined time period, deactivating the excitation voltage, and monitoring the voltage (VEMF) generated due to electro-motive force (EMF) across the coil. The polarity of VEMF changes when the rotor has moved a known distance—typically 90°. After detecting a polarity change, a negative excitation voltage is applied across the coil, deactivated, and VEMF monitored to detect a polarity change. This sequence is repeated to maintain the rotation of the rotor. The motor is preferably set into motion using a start-up routine, which also determines the predetermined time period used during steady-state operation.

Abstract: A method and system for providing sensorless brushless DC motor control using predictive switch timing requires connecting a stator coil in a bridge configuration, applying a positive excitation voltage across the coil for a predetermined time period, deactivating the excitation voltage, and monitoring the voltage (VEMF) generated due to electro-motive force (EMF) across the coil. The polarity of VEMF changes when the rotor has moved a known distance—typically 90°. After detecting a polarity change, a negative excitation voltage is applied across the coil, deactivated, and VEMF monitored to detect a polarity change. This sequence is repeated to maintain the rotation of the rotor. The motor is preferably set into motion using a start-up routine, which also determines the predetermined time period used during steady-state operation.