Patents by Inventor Naveen Batra
Naveen Batra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10468095Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.Type: GrantFiled: May 24, 2018Date of Patent: November 5, 2019Assignee: STMicroelectronics International N.V.Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
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Publication number: 20180268895Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.Type: ApplicationFiled: May 24, 2018Publication date: September 20, 2018Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
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Patent number: 10008258Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.Type: GrantFiled: October 18, 2016Date of Patent: June 26, 2018Assignee: STMicroelectronics International N.V.Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
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Publication number: 20170040052Abstract: A circuit can be used, for example, with a multi-supply memory device. The circuit includes a first conductor and a second conductor. A first transistor has a current path coupled between the first conductor and the second conductor. A second transistor also has a current path coupled between the first conductor and the second conductor. A pulse generator circuit has an input coupled to a control terminal of the first transistor and an output coupled to a control terminal of the second transistor.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Inventors: Piyush JAIN, Vivek ASTHANA, Naveen BATRA
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Patent number: 9508405Abstract: A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and the second pre-charge circuit are coupled between the bit line and the complementary bit line. The first pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a first voltage level. The second pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the first voltage level. In some examples, two precharge circuits are configured to operate such that memory access is ensured to be static noise margin safe even under wider difference between two voltage levels.Type: GrantFiled: October 3, 2013Date of Patent: November 29, 2016Assignee: STMicroelectronics International N.V.Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
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Publication number: 20150098267Abstract: A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and the second pre-charge circuit are coupled between the bit line and the complementary bit line. The first pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a first voltage level. The second pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the first voltage level. In some examples, two precharge circuits are configured to operate such that memory access is ensured to be static noise margin safe even under wider difference between two voltage levels.Type: ApplicationFiled: October 3, 2013Publication date: April 9, 2015Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Piyush JAIN, Vivek ASTHANA, Naveen BATRA
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Patent number: 8780615Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.Type: GrantFiled: March 16, 2012Date of Patent: July 15, 2014Assignee: STMicroelectronics International N.V.Inventors: Naveen Batra, Rajiv Kumar, Saurabh Agrawal
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Publication number: 20120224440Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.Type: ApplicationFiled: March 16, 2012Publication date: September 6, 2012Applicant: STMicroelectronics PVT LTD (INDIA)Inventors: Naveen BATRA, Rajiv Kumar, Saurabh Agrawal
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Patent number: 8259486Abstract: A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.Type: GrantFiled: September 30, 2009Date of Patent: September 4, 2012Assignee: STMicroelectronics International N.V.Inventors: Ashish Kumar, Naveen Batra
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Patent number: 8154911Abstract: A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.Type: GrantFiled: April 19, 2010Date of Patent: April 10, 2012Assignee: STMicroelectronics Pvt. Ltd.Inventors: Naveen Batra, Rajiv Kumar, Saurabh Agrawal
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Publication number: 20110149662Abstract: A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.Type: ApplicationFiled: April 19, 2010Publication date: June 23, 2011Applicant: STMICROELECTRONICS Pvt. Ltd.Inventors: Naveen BATRA, Rajiv Kumar, Saurabh Agrawal
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Publication number: 20110026309Abstract: A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.Type: ApplicationFiled: September 30, 2009Publication date: February 3, 2011Applicant: STMicroelectronics Pvt. Ltd.Inventors: Ashish KUMAR, Naveen Batra
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Publication number: 20100115385Abstract: An embodiment of the present disclosure relates to detection of data access element selection errors during data access in data storage arrays. An embodiment of the disclosure describes a system including a data storage array comprising a first and a second error identifier. The error identifiers generate an error signal in case multiple data access elements are selected or no data access element is selected, respectively. A system for detection of data-access-element-selection errors further comprises a common error-signal generator which provides an output when an error signal is generated by either of said error identifiers.Type: ApplicationFiled: November 5, 2009Publication date: May 6, 2010Applicant: STMICROELECTRONICS PVT. LTD.Inventors: NAVEEN BATRA, JITENDRA DASANI