Patents by Inventor Naveen K

Naveen K has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154741
    Abstract: An apparatus for a communication device, the apparatus may include a processor configured to: obtain channel metrics for a plurality of radio communication channels, each obtained channel metric is associated with a respective radio communication channel of the plurality of radio communication channels, generate a plurality of channel hopping sequences, each channel hopping sequence is representative of an allocation of the plurality of radio communication channels for a plurality of time slots, wherein a number of time slots allocated for each radio communication channel within each channel hopping sequence is based on the respective obtained channel metric, and select one of the plurality of channel hopping sequences based on a predefined criterion to communicate with a further communication device.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 9, 2024
    Inventors: Anshu AGARWAL, Kaushal BILLORE, Suranjan CHAKRABORTY, Amit Singh CHANDEL, Prasanna DESAI, Chandrashekar GOWDA, Vishal DHULL, Mallari HANCHATE, Mythili HEGDE, Vishnu K, Srinivas KROVVIDI, Naveen MANOHAR, Mayur MAHESHWARI, Yogesh MALKHEDE, Barath C. PETIT, Balvinder Pal SINGH, Sudhakaran SUBRAMANIAN, Rahul TIWARI, Padmavathi TIWARI, Divya Lakshmi Saranya VEMURI, Ingolf KARLS, Ehud RESHEF
  • Patent number: 11977885
    Abstract: An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 7, 2024
    Assignee: INTEL CORPORATION
    Inventors: Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei, Durgesh Borkar, Shubra Marwaha, Supratim Pal, Varghese George, Wei Xiong, Yan Li, Yongsheng Liu, Dipankar Das, Sasikanth Avancha, Dharma Teja Vooturi, Naveen K. Mellempudi
  • Publication number: 20240126544
    Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Dipankar DAS, Naveen K. MELLEMPUDI, Mrinmay DUTTA, Arun KUMAR, Dheevatsa MUDIGERE, Abhisek KUNDU
  • Publication number: 20240101630
    Abstract: Disclosed herein are immunomodulatory fusion proteins comprising an IL-2; an IL-12, a collagen-binding domain, and a linear polypeptide spacer, methods of making and using the same. The immunomodulatory fusion proteins disclosed herein are useful for the treatment of cancer.
    Type: Application
    Filed: December 17, 2021
    Publication date: March 28, 2024
    Inventors: Naveen Mehta, Jennifer Michaelson, Patrick Baeuerle, Li Bochong, Dane K. Wittrup
  • Patent number: 11927982
    Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 12, 2024
    Assignee: INTEL CORPORATION
    Inventors: Gururaj K. Shamanna, Naveen Kumar M, Harishankar Sahu, Abhishek Chouksey, Madhusudan Rao
  • Publication number: 20240080329
    Abstract: An illustrative method for performing a risk scenario assessment and remediation may include identifying, based on posture data associated with a compute environment, one or more compute resources deployed in the compute environment that are configured to be connected to a network, accessing runtime workload data associated with the one or more compute resources representative of network activity for the one or more compute resources, and performing, based on the posture data and the runtime workload data, a remediation operation associated with the one or more compute resources.
    Type: Application
    Filed: April 26, 2023
    Publication date: March 7, 2024
    Inventors: Theodore M. Reed, Nolan K. Karpinski, Xiaofei Guo, Christopher Hall, John Payyappillil John, Matti A. Vanninen, Naveen Kumar Bibinagar, Yijou Chen, Sowmya A. Karmali
  • Publication number: 20240076239
    Abstract: Stucco-cement compositions with a shortened drying time, lighter weight, high strength and reduced expansion, the compositions comprising expanded perlite and preferably also calcium aluminate cement and/or calcium sulfoaluminate cement, and methods for making and using these compositions, including pourable and/or pumpable floor underlayment slurries and methods for forming high strength underlayment on different substrates.
    Type: Application
    Filed: March 2, 2023
    Publication date: March 7, 2024
    Inventors: Sriram K. Valluri, David D. Pelot, Naveen Punati, Derik Harlow, Scott Cimaglio, Karl G. Niessner
  • Patent number: 11900107
    Abstract: Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Dipankar Das, Naveen K. Mellempudi, Mrinmay Dutta, Arun Kumar, Dheevatsa Mudigere, Abhisek Kundu
  • Publication number: 20230351542
    Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to convert elements of a floating-point tensor to convert the floating-point tensor into a fixed-point tensor.
    Type: Application
    Filed: April 24, 2023
    Publication date: November 2, 2023
    Applicant: Intel Corporation
    Inventors: Naveen K. MELLEMPUDI, DHEEVATSA MUDIGERE, DIPANKAR DAS, SRINIVAS SRIDHARAN
  • Publication number: 20230291790
    Abstract: During web application development, receiving a request for a webpage for a business object type, the request comprising a business object type identifier of the business object type, receiving an expression for selecting an instance of the first business object type from a plurality of instances of the first business object type, the expression specifying a data source and an operation. The method can further comprise generating the webpage, the webpage comprising a user interface (UI) widget for the business object type and an instruction for prepopulating the first UI widget with data from the instance of the first business object type, the instruction including the expression, the expression executable to perform an action on data from the data source to generate a result identifying the instance of the first business object type.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Inventors: Naveen K. Vidyananda, Sachin Gopaldas Totale
  • Patent number: 11689609
    Abstract: During web application development, receiving a request for a webpage for a first business object type, the first request comprising a first business object type identifier of the first business object type, receiving a first expression for selecting an instance of the first business object type from a plurality of instances of the first business object type from an object data source, the expression specifying a first data source and an operation and generating the webpage, the webpage comprising a first user interface (UI) widget for the first business object type and a first instruction for prepopulating the first UI widget with first data from the instance of the first business object type, the first instruction including the first expression, the first expression executable to perform the operation on data from the first data source to generate a result identifying the instance of the first business object type.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 27, 2023
    Assignee: Open Text Corporation
    Inventors: Naveen K. Vidyananda, Sachin Gopaldas Totale
  • Patent number: 11669933
    Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to quantize elements of a floating-point tensor to convert the floating-point tensor into a dynamic fixed-point tensor.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Naveen K. Mellempudi, Dheevatsa Mudigere, Dipankar Das, Srinivas Sridharan
  • Publication number: 20230040528
    Abstract: In some aspects, the disclosure provides compositions and methods for detecting and monitoring the activity of proteases in vivo using affinity assays. The disclosure relates, in part, to the discovery that biomarker nanoparticles targeted to the lymph nodes of a subject are useful for the diagnosis and monitoring of certain medical conditions (e.g., metastatic cancer, infection with certain pathogenic agents).
    Type: Application
    Filed: August 2, 2022
    Publication date: February 9, 2023
    Applicant: Massachusetts Institute of Technology
    Inventors: Sangeeta N. Bhatia, Darrell J. Irvine, Karl Dane Wittrup, Andrew David Warren, Jaideep S. Dudani, Naveen K. Mehta
  • Publication number: 20220387961
    Abstract: A method for chemical production includes applying electromagnetic heating to a composition that includes a catalytic component and an electromagnetic susceptor. Responsive to application of radio frequency energy, the electromagnetic susceptor causes the catalytic component to become heated. The heated electromagnetic susceptor and catalytic component interact with a chemical to form a product.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 8, 2022
    Inventors: Micah J. Green, Naveen K. Mishra, Nutan S. Patil, Benjamin A. Wilhite
  • Patent number: 11496398
    Abstract: An ingress fabric endpoint coupled to a switch fabric within a network device reorders packet flows based on congestion status. In one example, the ingress fabric endpoint receives packet flows for switching across the switch fabric. The ingress fabric endpoint assigns each packet for each packet flow to a fast path or a slow path for packet switching. The ingress fabric endpoint processes, to generate a stream of cells for switching across the switch fabric, packets from the fast path and the slow path to maintain a first-in-first-out ordering of the packets within each packet flow. The ingress fabric endpoint switches a packet of a first packet flow after switching a packet of a second packet flow despite receiving the packet of the first packet flow before the packet of the second packet flow.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: November 8, 2022
    Assignee: JUNIPER NETWORKS, INC.
    Inventors: Anuj Kumar Srivastava, Gary Goldman, Harshad B Agashe, Dinesh Jaiswal, Piyush Jain, Naveen K Jain
  • Publication number: 20220343174
    Abstract: Described herein is a graphics processor including a processing resource including a multiplier configured to multiply input associated with the instruction at one of a first plurality of bit widths, an adder configured to add a product output from the multiplier with an accumulator value at one of a second plurality of bit widths, and circuitry to select a first bit width of the first plurality of bit widths for the multiplier and a second bit width of the second plurality of bit widths for the adder.
    Type: Application
    Filed: May 12, 2022
    Publication date: October 27, 2022
    Applicant: Intel Corporation
    Inventors: Dipankar Das, Roger Gramunt, Mikhail Smelyanskiy, Jesus Corbal, Dheevatsa Mudigere, Naveen K. Mellempudi, Alexander F. Heinecke
  • Publication number: 20220337658
    Abstract: During web application development, receiving a request for a webpage for a first business object type, the first request comprising a first business object type identifier of the first business object type, receiving a first expression for selecting an instance of the first business object type from a plurality of instances of the first business object type from an object data source, the expression specifying a first data source and an operation and generating the webpage, the webpage comprising a first user interface (UI) widget for the first business object type and a first instruction for prepopulating the first UI widget with first data from the instance of the first business object type, the first instruction including the first expression, the first expression executable to perform the operation on data from the first data source to generate a result identifying the instance of the first business object type.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Naveen K. Vidyananda, Sachin Gopaldas Totale
  • Publication number: 20220327656
    Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to quantize elements of a floating-point tensor to convert the floating-point tensor into a dynamic fixed-point tensor.
    Type: Application
    Filed: April 27, 2022
    Publication date: October 13, 2022
    Applicant: Intel Corporation
    Inventors: Naveen K. MELLEMPUDI, DHEEVATSA MUDIGERE, DIPANKAR DAS, SRINIVAS SRIDHARAN
  • Patent number: 11448643
    Abstract: In some aspects, the disclosure provides compositions and methods for detecting and monitoring the activity of pro teases in vivo using affinity assays. The disclosure relates, in part, to the discovery that biomarker nanoparticles targeted to the lymph nodes of a subject are useful for the diagnosis and monitoring of certain medical conditions (e.g., metastatic cancer, infection with certain pathogenic agents).
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: September 20, 2022
    Assignee: Massachusetts Institute of Technology
    Inventors: Sangeeta N. Bhatia, Darrell J. Irvine, Karl Dane Wittrup, Andrew David Warren, Jaideep S. Dudani, Naveen K. Mehta
  • Patent number: 11412031
    Abstract: During web application development, receiving a request for a webpage for a first business object type, the first request comprising a first business object type identifier of the first business object type, receiving a first expression for selecting an instance of the first business object type from a plurality of instances of the first business object type from an object data source, the expression specifying a first data source and an operation and generating the webpage, the webpage comprising a first user interface (UI) widget for the first business object type and a first instruction for prepopulating the first UI widget with first data from the instance of the first business object type, the first instruction including the first expression, the first expression executable to perform the operation on data from the first data source to generate a result identifying the instance of the first business object type.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 9, 2022
    Assignee: OPEN TEXT CORPORATION
    Inventors: Naveen K. Vidyananda, Sachin Gopaldas Totale