Patents by Inventor NAVEEN VITTAL PRABHU
NAVEEN VITTAL PRABHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230062668Abstract: Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.Type: ApplicationFiled: August 25, 2021Publication date: March 2, 2023Inventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Sandeep Rasoori, Trupti Bemalkhedkar
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Publication number: 20210141703Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 24, 2020Publication date: May 13, 2021Applicant: Intel CorporationInventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Rohit Shenoy, Shankar Natarajan, Arun S. Athreya
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Patent number: 10891072Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.Type: GrantFiled: March 23, 2020Date of Patent: January 12, 2021Assignee: Micron Technology, Inc.Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
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Publication number: 20200301601Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.Type: ApplicationFiled: March 23, 2020Publication date: September 24, 2020Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
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Patent number: 10762974Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: June 3, 2019Date of Patent: September 1, 2020Assignee: Micron Technology, Inc.Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Patent number: 10599362Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.Type: GrantFiled: May 20, 2019Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
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Publication number: 20200090743Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.Type: ApplicationFiled: October 4, 2019Publication date: March 19, 2020Inventors: Aliasgar S. MADRASWALA, Bharat M. PATHAK, Binh N. NGO, Naveen VITTAL PRABHU, Karthikeyan RAMAMURTHI, Pranav KALAVADE
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Publication number: 20200019337Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.Type: ApplicationFiled: May 20, 2019Publication date: January 16, 2020Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
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Publication number: 20190355431Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: June 3, 2019Publication date: November 21, 2019Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Patent number: 10438656Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.Type: GrantFiled: December 18, 2017Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Aliasgar S. Madraswala, Bharat M. Pathak, Binh N. Ngo, Naveen Vittal Prabhu, Karthikeyan Ramamurthi, Pranav Kalavade
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Patent number: 10354738Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: September 27, 2017Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Patent number: 10331377Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.Type: GrantFiled: November 1, 2017Date of Patent: June 25, 2019Assignee: Micron Technology, Inc.Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
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Publication number: 20190163403Abstract: A method performed by a non volatile memory is described. The method includes receiving a first command from a controller to perform an operation. The method also includes receiving a second command from the controller to perform a read operation, where, the controller does not send a third command to suspend the operation between the first and second commands.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Aliasgar S. MADRASWALA, Naveen Vittal PRABHU
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Publication number: 20190129648Abstract: Devices and techniques for NAN flash thermal alerting are disclosed herein. A NAND array operation is received at a controller of a storage device that includes a NAND array. The controller evaluates a thermal condition of the NAND array in response to receipt of the NAND array operation. The controller then communicates the thermal condition along with a result of the NAND array operation.Type: ApplicationFiled: November 1, 2017Publication date: May 2, 2019Inventors: Naveen Vittal Prabhu, Aliasgar S. Madraswala, Simon Ramage
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Patent number: 10268407Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.Type: GrantFiled: September 29, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Aliasgar S. Madraswala, Xin Guo, Naveen Vittal Prabhu, Yu Du, Purval Shyam Sule
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Publication number: 20190102097Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: Aliasgar S. Madraswala, Xin Guo, Naveen Vittal Prabhu, Yu Du, Purval Shyam Sule
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Publication number: 20190096494Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventors: Aliasgar S. Madraswala, Kristopher H. Gaewsky, Naveen Vittal Prabhu, Purval S. Sule, Trupti Bemalkhedkar, Nehul N. Tailor, Quan H. Ngo, Dheeraj Srinivasan
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Publication number: 20190043564Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.Type: ApplicationFiled: December 18, 2017Publication date: February 7, 2019Applicant: Intel CorporationInventors: ALIASGAR S. MADRASWALA, BHARAT M. PATHAK, BINH N. NGO, NAVEEN VITTAL PRABHU, KARTHIKEYAN RAMAMURTHI, PRANAV KALAVADE
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Publication number: 20190042130Abstract: A system for reconfiguring flash memory from a default access operation mode (e.g., MLC, TLC, or QLC mode) to a non-default access operation mode (e.g., SLC mode) using opcode prefixes is provided. Opcode prefix logic enables the flash memory die to enter a non-default (e.g., faster) access operation mode. The non-default access operation mode is entered by providing a prefix instruction or opcode prefix to the memory controller and/or to the flash memory die prior to memory operation commands (“opcode”) for program, read, and/or erase. The flash memory die is configured to automatically exit the non-default access operation mode after a single operation, or the flash memory die is configured to exit the non-default access operation mode upon receipt of another opcode prefix.Type: ApplicationFiled: December 18, 2017Publication date: February 7, 2019Applicant: Intel CorporationInventors: NAVEEN VITTAL PRABHU, ALIASGAR S. MADRASWALA, DONIA SEBASTIAN, SHANKAR NATARAJAN