Abstract: A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (?) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series between source terminals of a thick-oxide drive transistor and a power rail to avoid explicit level-shifting circuitry between the relatively low core voltage domain and relatively high I/O voltage domain.

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

Abstract: A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

Abstract: In a delay control circuit having a plurality of series-coupled delay stages, an input signal is routed through one of the series-coupled delay stages via a first delay element if a first delay control value is in a first state, the first delay element imposing a first signal propagation delay according to a first bias signal. If the delay control value is in a second state, the input signal is routed through the one of the series-coupled delay stages via a second delay element instead of the first delay element, the second delay element imposing a second signal propagation delay according to a second bias signal. The first and second bias signals are calibrated such that the second signal propagation delay exceeds the first propagation delay by a predetermined time interval that is substantially briefer than the first signal propagation delay.

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be245 adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

Abstract: A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.

Abstract: A gating signal for masking overhead transitions in a timing signal is generated adaptively based on timing events in the incoming timing signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the timing signal.

Abstract: A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.

Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

Abstract: A method of operation in a memory controller includes operating pull-up and pull-down drivers driven by separate pre-drivers between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based on both the pull-up driver and the pull-down driver.

Abstract: A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal.

Abstract: A method of operation in a memory controller includes operating pull-up and pull-down drivers driven by separate pre-drivers between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based on both the pull-up driver and the pull-down driver.

Abstract: A driver circuit includes pull-up and pull-down drivers driven by separate pre-drivers operating between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based on both the pull-up driver and the pull-down driver.

Abstract: A driver circuit includes pull-up and pull-down drivers driven by separate pre-drivers operating between different voltage rails. Data signals driving the pull-up driver and the pull-down driver are synchronized, and the pull-up driver and the pull-down driver are coupled together to produce an output signal having a voltage swing based on both the pull-up driver and the pull-down driver.