Patents by Inventor Navneeth Kankani
Navneeth Kankani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11010074Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.Type: GrantFiled: March 23, 2020Date of Patent: May 18, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Navneeth Kankani, Linh Tien Truong
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Patent number: 10884629Abstract: A performance metric of a data shard stored in a first storage portion is monitored. It is determined that the performance metric of the data shard exceeds a threshold. In response to the determination that the performance metric exceeds the threshold, the data shard is reassigned to a second storage portion selected based on an over-provisioning bias of the second storage portion that is different than an over-provisioning bias of the first storage portion or the over-provisioning bias of the first storage portion is increased.Type: GrantFiled: February 27, 2019Date of Patent: January 5, 2021Assignee: Facebook, Inc.Inventors: Navneeth Kankani, Mrinmoy Ghosh
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Publication number: 20200218460Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.Type: ApplicationFiled: March 23, 2020Publication date: July 9, 2020Inventors: Navneeth KANKANI, Linh Tien TRUONG
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Patent number: 10642517Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.Type: GrantFiled: March 13, 2018Date of Patent: May 5, 2020Assignee: Western Digital Technologies, Inc.Inventors: Navneeth Kankani, Linh Tien Truong
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Patent number: 10509598Abstract: Systems and methods are disclosed for writing data to a non-volatile memory (NVM) using a segmented write process. The NVM uses a plurality of program loops to write data to the NVM. The NVM groups the plurality of program loops into a plurality of write segments, and each write segment includes a distinct set of the plurality of program loops. The write segments are separated by a dwell time that allows read access before the data is written to the NVM.Type: GrantFiled: February 15, 2018Date of Patent: December 17, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Navneeth Kankani, Sarath Chandran Puthen Thermadam, Namasivayam Raghunathan
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Patent number: 10467134Abstract: Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature.Type: GrantFiled: August 25, 2016Date of Patent: November 5, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Navneeth Kankani, Linh Truong, Sarath Puthenthermadam, Deepanshu Dutta
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Publication number: 20190250851Abstract: Systems and methods are disclosed for writing data to a non-volatile memory (NVM) using a segmented write process. The NVM uses a plurality of program loops to write data to the NVM. The NVM groups the plurality of program loops into a plurality of write segments, and each write segment includes a distinct set of the plurality of program loops. The write segments are separated by a dwell time that allows read access before the data is written to the NVM.Type: ApplicationFiled: February 15, 2018Publication date: August 15, 2019Inventors: Navneeth Kankani, Sarath Chandran Puthen Thermadam, Namasivayam Raghunathan
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Publication number: 20190243567Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.Type: ApplicationFiled: March 13, 2018Publication date: August 8, 2019Inventors: Navneeth KANKANI, Linh Tien Truong
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Patent number: 10026492Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.Type: GrantFiled: July 2, 2017Date of Patent: July 17, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Arash Hazeghi, Huai-Yuan Tseng, Cynthia Hsu, Navneeth Kankani
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Publication number: 20180060230Abstract: Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature.Type: ApplicationFiled: August 25, 2016Publication date: March 1, 2018Applicant: SanDisk Technologies LLCInventors: Navneeth Kankani, Linh Truong, Sarath Puthenthermadam, Deepanshu Dutta
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Patent number: 9898364Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.Type: GrantFiled: November 17, 2014Date of Patent: February 20, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: James M. Higgins, Robert W. Ellis, Neil R. Darragh, Aaron K. Olbrich, Navneeth Kankani, Steven Sprouse
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Patent number: 9891844Abstract: Systems, methods, and/or devices are used to implement variable bit encoding to improve device endurance and extend life of storage devices. In some embodiments, the method includes determining a current endurance metric for a plurality of non-volatile memory portions configured to store data encoded in a first encoding format and determining an estimated endurance metric for the plurality of non-volatile memory portions (e.g., corresponding to estimated endurance after reconfiguration of the one or more portions to store data encoded in a second encoding format), and in accordance with a determination that reconfiguration criteria are satisfied (e.g., the estimated endurance metric comprises an improvement over the current endurance metric), reconfiguring the one or more portions to store data encoded in the second encoding format.Type: GrantFiled: April 11, 2017Date of Patent: February 13, 2018Assignee: SanDisk Technologies LLCInventors: Navneeth Kankani, Linh Tien Truong
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Patent number: 9864525Abstract: Systems, methods, and/or devices are used to implement variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format and having a first storage density) of a plurality of non-volatile memory portions of a storage device. In response to detecting the trigger condition and in accordance with a first determination that a projected amount of over-provisioning (e.g., corresponding to over-provisioning for the storage device after reconfiguring the one or more non-volatile memory portions to store data encoded in a second encoding format and having a second storage density) meets predefined over-provisioning criteria, the method includes reconfiguring the one or more non-volatile memory portions to store data encoded in the second encoding format.Type: GrantFiled: February 24, 2017Date of Patent: January 9, 2018Assignee: SanDisk Technologies LLCInventors: Navneeth Kankani, Linh Tien Truong
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Publication number: 20170309344Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.Type: ApplicationFiled: July 2, 2017Publication date: October 26, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Arash Hazeghi, Huai-Yuan Tseng, Cynthia Hsu, Navneeth Kankani
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Patent number: 9761290Abstract: Apparatuses, systems, methods, and computer program products are disclosed for preventing overheating, for annealing non-volatile memory. An apparatus may include an array of non-volatile storage elements. A heating element may be configured to heat a first set of the non-volatile storage elements to anneal the first set of non-volatile storage elements. A heat shield or cooling element may be configured to prevent a second set of the non-volatile storage elements from overheating during annealing of the first set of non-volatile storage elements, to mitigate data errors for data stored on the second set of non-volatile storage elements.Type: GrantFiled: August 25, 2016Date of Patent: September 12, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Navneeth Kankani, Ning Ye, Suresh Upadhyayula, Sarath Puthenthermadam, Deepanshu Dutta
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Publication number: 20170220269Abstract: Systems, methods, and/or devices are used to implement variable bit encoding to improve device endurance and extend life of storage devices. In some embodiments, the method includes determining a current endurance metric for a plurality of non-volatile memory portions configured to store data encoded in a first encoding format and determining an estimated endurance metric for the plurality of non-volatile memory portions (e.g., corresponding to estimated endurance after reconfiguration of the one or more portions to store data encoded in a second encoding format), and in accordance with a determination that reconfiguration criteria are satisfied (e.g., the estimated endurance metric comprises an improvement over the current endurance metric), reconfiguring the one or more portions to store data encoded in the second encoding format.Type: ApplicationFiled: April 11, 2017Publication date: August 3, 2017Inventors: Navneeth Kankani, Linh Tien Truong
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Patent number: 9721672Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.Type: GrantFiled: April 15, 2016Date of Patent: August 1, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Arash Hazeghi, Huai-Yuan Tseng, Cynthia Hsu, Navneeth Kankani
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Publication number: 20170168713Abstract: Systems, methods, and/or devices are used to implement variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format and having a first storage density) of a plurality of non-volatile memory portions of a storage device. In response to detecting the trigger condition and in accordance with a first determination that a projected amount of over-provisioning (e.g., corresponding to over-provisioning for the storage device after reconfiguring the one or more non-volatile memory portions to store data encoded in a second encoding format and having a second storage density) meets predefined over-provisioning criteria, the method includes reconfiguring the one or more non-volatile memory portions to store data encoded in the second encoding format.Type: ApplicationFiled: February 24, 2017Publication date: June 15, 2017Inventors: Navneeth Kankani, Linh Tien Truong
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Patent number: 9645749Abstract: A storage system includes a memory controller and a storage device with one or more memory devices, each with a plurality of memory portions. The memory controller determines an initial storage capacity for each of the one or more memory devices, where the one or more memory devices are configured in a first storage density. The memory controller detects a trigger condition as to at least one memory portion of a respective device of the one or more memory devices and, in response to detecting the trigger condition, recharacterizes the at least one memory portion of the respective memory device so as to be configured in a second storage density, where the at least one recharacterized memory portion of the respective memory device has a reduced storage capacity. After the recharacterizing, the memory controller determines a revised storage capacity for the respective memory device.Type: GrantFiled: July 1, 2014Date of Patent: May 9, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Linh Tien Truong, Allen Samuels, Navneeth Kankani
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Patent number: 9639282Abstract: Systems, methods, and/or devices are used to implement variable bit encoding to improve device endurance and extend life of storage devices. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format) of a plurality of non-volatile memory portions of a storage device. In accordance with detecting the trigger condition, the method includes: determining a current and an estimated endurance metric for the plurality of non-volatile memory portions (e.g., corresponding to estimated endurance after reconfiguration of the one or more portions to store data encoded in a second encoding format), and in accordance with a determination that reconfiguration criteria are satisfied (e.g., the estimated endurance metric comprises an improvement over the current endurance metric), reconfiguring the one or more portions to store data encoded in the second encoding format.Type: GrantFiled: October 30, 2015Date of Patent: May 2, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Navneeth Kankani, Linh Tien Truong