Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Abstract: It has been discovered that initialization of a memory array can be improved by setting the nodes of the memory array to a predetermined value automatically upon applying power to the integrated circuit. Data input nodes and a memory write enable node are configured to store the predetermined values on the nodes of the memory array in response to successive enablement of word lines corresponding to the nodes of the memory array and automatic reset of the word lines. Circuitry included for initializing control and data signals of the memory array are effectively disabled upon termination of the initialization. Inclusion of circuitry that initiates and terminates the initialization obviates an additional input/output pin for this purpose.

Abstract: A method of transmitting and prioritizing signals is disclosed. Higher priority signals are switched while lower priority signals are delayed until the higher priority signals have completed switching. The method is used in networks where coupling and capacitance effects are possible.

Abstract: Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.

Abstract: A stable and accurate level shifter for converting voltage levels of signals in CMOS devices. In one embodiment of the invention, the level shifter comprises two legs having transistors operably connected in a source-follower configuration. The biasing of the level shifter is provided by a multistage biasing circuit that comprises a plurality of N-MOS devices. The biasing source can be operated with a single stage or can be configured to combine multiple stages to increase the current (voltage) provided by the biasing circuit. The level shifter of the present invention consumes less power and requires less area on an integrated circuit than prior art level shifters. In addition, the level shifter is insensitive to negative bias temperature instability (NBTI) effects, thereby allowing the level shifter to be highly reliable throughout the life of the part with minimal degradation in the performance and accuracy of the level shifter through time.

Abstract: Provided are a method and a system to distribute clock signals in digital circuits to ensure that the multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an off-chip set of clock paths, which includes one or more clock buffers, are connected between two sets of clock paths on an integrated digital circuit. The multiple clock signals are routed to the off-chip set of clock paths to reduce, or remove, propagational delay in multiple clock signals that arise from the propagation of the same through the on-chip clock paths. This is achieved by the clock paths of the off-chip set of clock paths having differing resistivities, differing lengths or both.

Abstract: A circuit package and a method of forming the same that facilitates control of the impedance of a driving circuit employing resistive vias formed into a dielectric substrate.

Abstract: Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.

Abstract: Provided are a method and a system to distribute clock signals in digital circuits to ensure that the multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an off-chip set of clock paths, which includes one or more clock buffers, are connected between two sets of clock paths on an integrated digital circuit. The multiple clock signals are routed to the off-chip set of clock paths to reduce, or remove, propagational delay in multiple clock signals that arise from the propagation of the same through the on-chip clock paths. This is achieved by the clock paths of the off-chip set of clock paths having differing resistivities, differing lengths or both.

Abstract: A circuit package and a method of forming the same that facilitates control of the impedance of a driving circuit employing resistive vias formed into a dielectric substrate.

Abstract: The present invention describes a method and an apparatus for zero skew signal transition detection between multiple communication paths. The signal transition at the transition point is detected by sampling the signal before the transition point. A transition detection pulse is generated when the signal begins to transition at the transition point. The transition detection pulse can be used to adjust the signal transition on multiple adjacent parallel paths with zero skew to obtain desired coupling between the paths. The width of transition detection pulse can be adjusted to match the transition period of the signal.

Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.

Abstract: A method of transmitting and prioritizing signals is disclosed. Higher priority signals are switched while lower priority signals are delayed until the higher priority signals have completed switching. The method is used in networks where coupling and capacitance effects are possible.