Abstract: An apparatus includes a circuit to generate a clock having a period with a duty cycle less than or equal to 90%, and logic to determine a difference in an input voltage between a first time and a second time, at least in part based on the duty cycle of the clock, and to produce a first signal, at least in part based on the difference in the input voltage and a first predetermined threshold.

Abstract: Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.

Abstract: Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.

Abstract: Methods and apparatus relating to techniques for mesh performance improvement using dual voltage data transfer are described. In one embodiment, a first plurality of signal paths are operated at a higher voltage level than a second plurality of signal paths. The first plurality of signal paths comprises Resistor-Capacitor (RC) dominated signal paths that move signals between any two system tiles. Other embodiments are also disclosed.

Abstract: Methods and apparatus relating to techniques for mesh performance improvement using dual voltage data transfer are described. In one embodiment, a first plurality of signal paths are operated at a higher voltage level than a second plurality of signal paths. The first plurality of signal paths comprises Resistor-Capacitor (RC) dominated signal paths that move signals between any two system tiles. Other embodiments are also disclosed.

Abstract: The present disclosure describes a circuit for managing power and heat. The circuit includes a voltage regulator, and a calibration module comprising logic, at least partially comprising hardware logic. The calibration module is configured to identify a first voltage of the circuit when a current is not provided to the voltage regulator, and determine a second voltage of the circuit when a current is provided to the voltage regulator during a reset sequence. The calibration module is further configured to compare the first voltage to the second voltage.

Abstract: A circuit for protecting internal logic circuits of an integrated circuit (IC) device from a failure of internal voltage supply is disclosed. A protection circuit is connected between the internal power supply and an external power supply. The protection circuit reduces the external power to the internal logic circuits. A pass circuit is connected to the protection circuit and the internal power supply. The pass circuit is configured to reduce the input voltage difference in the protection circuit in the event of a failure of the internal power supply to prevent a failure of the protection circuit. The voltage level of the external power supply is typically higher than the internal supply voltage level, and exposure to the full external voltage level may disable the protection circuit.

Abstract: Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

Abstract: A circuit for driving GTL-type buses actively drives a bus trace towards a first reference voltage when a signal in a first voltage state is detected at its input and actively drives the bus trace towards a second reference voltage for a selected period when the signal at its input transitions from the first voltage state to a second voltage state. The circuit includes a flip-flop for storing the sequential voltage states of the signal, logic for comparing the current voltage state of the signal with a replica of the preceding voltage state of the signal, and first and second transistors of complementary conductivity types, for driving the bus trace to first or second reference voltages, respectively, when activated. The first transistor is turned on when the signal is in the first voltage state.

Abstract: A circuit for protecting internal logic circuits of an integrated circuit (IC) device from a failure of internal voltage supply is disclosed. A protection circuit is connected between the internal power supply and an external power supply. The protection circuit reduces the external power to the internal logic circuits. A pass circuit is connected to the protection circuit and the internal power supply. The pass circuit is configured to reduce the input voltage difference in the protection circuit in the event of a failure of the internal power supply to prevent a failure of the protection circuit. The voltage level of the external power supply is typically higher than the internal supply voltage level, and exposure to the full external voltage level may disable the protection circuit.